公开(公告)号：US10115462B2

公开(公告)日：2018-10-30

申请号：US15474607

申请日：2017-03-30

Applicant: STMicroelectronics S.r.l.

Inventor： Salvatore Polizzi ,  Maurizio Francesco Perroni

IPC: G11C13/00

Abstract: An address decoder, for a non-volatile memory device provided with a memory array having memory cells arranged in word lines (WL) and bit lines (BL), each memory cell being having a memory element and an access element with a MOS transistor for enabling access to the memory element. Source terminals of the MOS transistors of the access elements of the memory cells of a same word line are connected to a respective source line. The address decoder has a row-decoder circuit and a column-decoder circuit, for selecting and biasing the word lines and the bit lines, respectively, of the memory array with row-driving signals (VWL) and column-driving signals (VBL), respectively. The address decoder has a source-decoder circuit for generating source-driving signals (VSL) for biasing the source lines of the memory array, on the basis of the logic combination of the row-driving signals of associated word lines.

公开(公告)号：US20180061495A1

公开(公告)日：2018-03-01

申请号：US15476003

申请日：2017-03-31

Applicant: STMicroelectronics S.r.l.

Inventor： Antonino Conte ,  Carmelo Paolino ,  Maurizio Francesco Perroni ,  Salvatore Polizzi

IPC: G11C16/12 ,  H03K19/0185 ,  G11C16/20 ,  G11C16/08 ,  G11C13/00 ,  G11C16/26

CPC classification number: G11C16/12 ,  G11C8/08 ,  G11C13/0004 ,  G11C16/08 ,  G11C16/20 ,  G11C16/26 ,  H03K3/356113 ,  H03K19/018521

Abstract: A level shifter circuit is designed to shift an input signal that switches within a first voltage range to supply an output signal that switches within a second voltage range, higher than the first voltage range. A first inverter stage has an input receiving the input signal and also has an output. A first capacitive element is connected between the output of the first input inverter stage and a first holding node. A latch stage is connected between the first holding node and a second holding node that is coupled to an output terminal, on which the output signal is present. The first input inverter stage is designed to operate in the first voltage range, and the latch stage is designed to operate in the second voltage range.

公开(公告)号：US20180047455A1

公开(公告)日：2018-02-15

申请号：US15795552

申请日：2017-10-27

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni Campardo ,  Salvatore Polizzi

IPC: G11C16/28 ,  G11C16/26 ,  G11C11/56 ,  G11C7/14 ,  G11C8/08 ,  G11C16/32 ,  G11C8/14

CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C7/14 ,  G11C7/227 ,  G11C8/08 ,  G11C8/14 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32

Abstract: A memory device includes a memory array with memory cells arranged in rows and columns and with word lines and bit lines. A dummy structure includes a dummy row of dummy cells and a dummy word line. A first pre-charging stage biases a word line of the memory array. An output stage includes a plurality of sense amplifiers. Each sense amplifier generates a corresponding output signal representing a datum stored in a corresponding memory cell pre-charged by the first pre-charging stage. A second pre-charging stage biases the dummy word line simultaneously with the word line biased by the first pre-charging stage. The output stage includes an enable stage, which detects a state of complete pre-charging of an intermediate dummy cell.

公开(公告)号：US10186317B2

公开(公告)日：2019-01-22

申请号：US15842347

申请日：2017-12-14

Applicant: STMicroelectronics S.r.l.

Inventor： Maurizio Francesco Perroni ,  Carmelo Paolino ,  Salvatore Polizzi

IPC: G11C13/00 ,  G11C17/18

Abstract: A phase change memory device includes two portions with local bitlines connected to memory cells. A reading stage is configured to read logic data stored by the first and second memory cells. A first main bitline extends between the reading stage and the first local bitlines and a first main switch is coupled between the first main bitline and reading stage and likewise for the second portion. Local switches are associated with respective ones of the local bitlines. A first reference signal generator is coupled to the reading stage. The phase change memory device is configured to operate in a first reading mode, in which the logic data stored by the first memory cell is read by the reading stage by comparison with the reference signal.

公开(公告)号：US20180096727A1

公开(公告)日：2018-04-05

申请号：US15474607

申请日：2017-03-30

Applicant: STMicroelectronics S.r.l.

Inventor： Salvatore Polizzi ,  Maurizio Francesco Perroni

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C8/10 ,  G11C11/1657 ,  G11C11/1659 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0097 ,  G11C2213/79 ,  G11C2213/82

Abstract: An address decoder, for a non-volatile memory device provided with a memory array having memory cells arranged in word lines (WL) and bit lines (BL), each memory cell being having a memory element and an access element with a MOS transistor for enabling access to the memory element. Source terminals of the MOS transistors of the access elements of the memory cells of a same word line are connected to a respective source line. The address decoder has a row-decoder circuit and a column-decoder circuit, for selecting and biasing the word lines and the bit lines, respectively, of the memory array with row-driving signals (VWL) and column-driving signals (VBL), respectively. The address decoder has a source-decoder circuit for generating source-driving signals (VSL) for biasing the source lines of the memory array, on the basis of the logic combination of the row-driving signals of associated word lines.

公开(公告)号：US09805810B1

公开(公告)日：2017-10-31

申请号：US15387397

申请日：2016-12-21

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni Campardo ,  Salvatore Polizzi

IPC: G11C7/00 ,  G11C16/28 ,  G11C16/24 ,  G11C16/08

CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C7/14 ,  G11C7/227 ,  G11C8/08 ,  G11C8/14 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32

Abstract: A memory device includes a memory array with memory cells arranged in rows and columns and with word lines and bit lines. A dummy structure includes a dummy row of dummy cells and a dummy word line. A first pre-charging stage biases a word line of the memory array. An output stage includes a plurality of sense amplifiers. Each sense amplifier generates a corresponding output signal representing a datum stored in a corresponding memory cell pre-charged by the first pre-charging stage. A second pre-charging stage biases the dummy word line simultaneously with the word line biased by the first pre-charging stage. The output stage includes an enable stage, which detects a state of complete pre-charging of an intermediate dummy cell.

公开(公告)号：US10002672B2

公开(公告)日：2018-06-19

申请号：US15795552

申请日：2017-10-27

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni Campardo ,  Salvatore Polizzi

IPC: G11C7/00 ,  G11C16/28 ,  G11C16/32 ,  G11C16/26 ,  G11C11/56 ,  G11C8/14 ,  G11C8/08 ,  G11C7/22 ,  G11C7/14 ,  G11C16/24 ,  G11C16/08 ,  G11C7/06

CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C7/14 ,  G11C7/227 ,  G11C8/08 ,  G11C8/14 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32

Abstract: A memory device includes a memory array with memory cells arranged in rows and columns and with word lines and bit lines. A dummy structure includes a dummy row of dummy cells and a dummy word line. A first pre-charging stage biases a word line of the memory array. An output stage includes a plurality of sense amplifiers. Each sense amplifier generates a corresponding output signal representing a datum stored in a corresponding memory cell pre-charged by the first pre-charging stage. A second pre-charging stage biases the dummy word line simultaneously with the word line biased by the first pre-charging stage. The output stage includes an enable stage, which detects a state of complete pre-charging of an intermediate dummy cell.

公开(公告)号：US09972394B2

公开(公告)日：2018-05-15

申请号：US15476003

申请日：2017-03-31

Applicant: STMicroelectronics S.r.l.

Inventor： Antonino Conte ,  Carmelo Paolino ,  Maurizio Francesco Perroni ,  Salvatore Polizzi

IPC: G11C16/12 ,  H03K19/0185 ,  G11C16/20 ,  G11C16/08 ,  G11C13/00 ,  G11C16/26

CPC classification number: G11C16/12 ,  G11C8/08 ,  G11C13/0004 ,  G11C16/08 ,  G11C16/20 ,  G11C16/26 ,  H03K3/356113 ,  H03K19/018521

Abstract: A level shifter circuit is designed to shift an input signal that switches within a first voltage range to supply an output signal that switches within a second voltage range, higher than the first voltage range. A first inverter stage has an input receiving the input signal and also has an output. A first capacitive element is connected between the output of the first input inverter stage and a first holding node. A latch stage is connected between the first holding node and a second holding node that is coupled to an output terminal, on which the output signal is present. The first input inverter stage is designed to operate in the first voltage range, and the latch stage is designed to operate in the second voltage range.

公开(公告)号：US09865356B2

公开(公告)日：2018-01-09

申请号：US15275362

申请日：2016-09-24

Applicant: STMicroelectronics S.r.l

Inventor： Giovanni Campardo ,  Salvatore Polizzi

IPC: G11C11/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C7/12 ,  G11C7/18 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/24 ,  G11C16/28 ,  G11C2207/002 ,  G11C2207/12

Abstract: A circuit for reading a memory cell of a non-volatile memory device provided with a memory array with cells arranged in wordlines and bitlines, among which a first bitline, associated to the memory cell, and a second bitline, has: a first circuit branch associated to the first bitline and a second circuit branch associated to the second bitline, each with a local node, coupled to which is a first dividing capacitor, and a global node, coupled to which is a second dividing capacitor; a decoder stage for coupling the local node to the first or second bitlines and coupling the global node to the local node; and a differential comparator stage supplies an output signal indicative of the datum stored; and a control unit for controlling the decoder stage, the coupling stage, and the differential comparator stage for generation of the output signal.

公开(公告)号：US09865346B1

公开(公告)日：2018-01-09

申请号：US15475609

申请日：2017-03-31

Applicant: STMicroelectronics S.r.l.

Inventor： Maurizio Francesco Perroni ,  Carmelo Paolino ,  Salvatore Polizzi

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0064 ,  G11C13/0069 ,  G11C17/18 ,  G11C2013/0042

Abstract: A phase change memory device includes two portions with local bitlines connected to memory cells. A reading stage is configured to read logic data stored by the first and second memory cells. A first main bitline extends between the reading stage and the first local bitlines and a first main switch is coupled between the first main bitline and reading stage and likewise for the second portion. Local switches are associated with respective ones of the local bitlines. A first reference signal generator is coupled to the reading stage. The phase change memory device is configured to operate in a first reading mode, in which the logic data stored by the first memory cell is read by the reading stage by comparison with the reference signal.