公开(公告)号：US20200227418A1

公开(公告)日：2020-07-16

申请号：US16732925

申请日：2020-01-02

Applicant: Samsung Electronics Co., ltd.

Inventor： Hui-Jung KIM ,  Min Hee CHO ,  Junsoo KIM ,  Taehyun An ,  Dongsoo Woo ,  Yoosang HWANG

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02

Abstract: A semiconductor memory device includes a stack structure having a plurality of layers vertically stacked on a substrate, each layer including, a first bit line and a gate line extending in a first direction, a first semiconductor pattern extending in a second direction between the first bit line and the gate line, the second direction intersecting the first direction, and a second semiconductor pattern adjacent to the gate line across a first gate insulating layer, the second semiconductor pattern extending in the first direction, a first word line adjacent to the first semiconductor pattern and vertically extending in a third direction from the substrate, a second bit line connected to an end of the second semiconductor pattern and vertically extending in the third direction from the substrate, and a second word line connected to another end of the second semiconductor pattern and vertically extending in the third direction.

公开(公告)号：US12029029B2

公开(公告)日：2024-07-02

申请号：US17716215

申请日：2022-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Hyuncheol Kim ,  Dongsoo Woo ,  Sungwon Yoo

IPC: H10B12/00 ,  H01L29/423 ,  H01L29/792

CPC classification number: H10B12/50 ,  H01L29/4234 ,  H01L29/7926

Abstract: A semiconductor memory device includes a semiconductor substrate a gate structure extending in a vertical direction on the semiconductor device, a plurality of charge trap layers spaced apart from each other in the vertical direction and each having a horizontal cross-section with a first ring shape surrounding the gate structure, a plurality of semiconductor patterns spaced apart from each other in the vertical direction and each having a horizontal cross-section with a second ring shape surrounding the plurality of charge trap layers, a source region and a source line at one end of each of the plurality of semiconductor patterns in a horizontal direction, and a drain region and a drain line at an other end of each of the plurality of semiconductor patterns in the horizontal direction. The gate structure may include a gate insulation layer and a gate electrode layer.

公开(公告)号：US12016188B2

公开(公告)日：2024-06-18

申请号：US17840213

申请日：2022-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Dongsoo Woo ,  Kyunghwan Lee

IPC: G11C13/00 ,  H10K10/50 ,  H10K19/00 ,  H10K85/20

CPC classification number: H10K19/202 ,  G11C13/0014 ,  G11C13/0069 ,  H10K10/50 ,  H10K85/221

Abstract: A semiconductor memory device includes a plurality of semiconductor patterns extending in a first horizontal direction and separated from each other in a second horizontal direction and a vertical direction, each semiconductor pattern including a first source/drain area, a channel area, and a second source/drain area arranged in the first horizontal direction; a plurality of gate insulating layers covering upper surfaces or side surfaces of the channel areas; a plurality of word lines on the upper surfaces or the side surfaces of the channel areas; and a plurality of resistive switch units respectively connected to first sidewalls of the semiconductor patterns, extending in the first horizontal direction, and separated from each other in the second horizontal direction and the vertical direction, each resistive switch unit including a first electrode, a second electrode, and a resistive switch material layer between the first and second electrodes and including carbon nanotubes.

公开(公告)号：US11968823B2

公开(公告)日：2024-04-23

申请号：US17716194

申请日：2022-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyejin Seong ,  Dongsoo Woo ,  Wonchul Lee

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/09 ,  H10B12/315 ,  H10B12/482 ,  H10B12/485 ,  H10B12/50

Abstract: A semiconductor memory device includes a substrate having a memory cell region where a plurality of active regions are defined; a word line having a stack structure of a lower word line layer and an upper word line layer and extending over the plurality of active regions in a first horizontal direction, and a buried insulation layer on the word line; a bit line structure arranged on the plurality of active regions, extending in a second horizontal direction perpendicular to the first horizontal direction, and having a bit line; and a word line contact plug electrically connected to the lower word line layer by penetrating the buried insulation layer and the upper word line layer and having a plug extension in an upper portion of the word line contact plug, the plug extension having a greater horizontal width than a lower portion of the word line contact plug.

公开(公告)号：US11856753B2

公开(公告)日：2023-12-26

申请号：US17837962

申请日：2022-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Jung Lee ,  Joon-Seok Moon ,  Dongsoo Woo

IPC: H10B12/00 ,  H01L29/06 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/49

CPC classification number: H10B12/34 ,  H01L21/28088 ,  H01L21/32133 ,  H01L29/0649 ,  H01L29/4966 ,  H10B12/053 ,  H10B12/315

Abstract: A semiconductor device, and a method of fabricating the semiconductor device including forming on a substrate a device isolation layer defining a plurality of active regions; and forming a plurality of gate lines intersecting the active regions and buried in the substrate. The forming of the gate lines includes forming on the substrate a trench that intersects the active regions; forming a work-function control layer on a sidewall and a bottom surface of the trench; forming a conductive layer on the work-function control layer; sequentially forming a barrier layer and a source layer on the work-function control layer and the conductive layer, the source layer including a work-function control element; and diffusing the work-function control element from the source layer into an upper portion of the work-function control layer.

公开(公告)号：US20230112070A1

公开(公告)日：2023-04-13

申请号：US17836228

申请日：2022-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjun Lee ,  Yongseok Kim ,  Hyuncheol Kim ,  Jongman Park ,  Dongsoo Woo ,  Kyunghwan Lee

IPC: G11C11/22 ,  G11C5/06

Abstract: Provided is a memory device. The memory device may include a substrate, a ferroelectric field effect transistor disposed on the substrate, a first channel contacting a gate structure of the ferroelectric field effect transistor and extending in a vertical direction from the gate structure of the ferroelectric field effect transistor, a selection word line disposed at one side of the first channel, a first gate dielectric layer disposed between the first channel and the selection word line, and a cell word line disposed on top of the first channel.

公开(公告)号：US11508733B2

公开(公告)日：2022-11-22

申请号：US16744871

申请日：2020-01-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungjun Noh ,  Junsoo Kim ,  Dongsoo Woo ,  Namho Jeon

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L27/108 ,  H01L29/66 ,  H01L21/285 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/528 ,  H01L29/51 ,  H01L21/3115 ,  H01L21/265 ,  H01L21/28 ,  H01L21/02 ,  H01L21/3065

Abstract: An integrated circuit device includes: a substrate including active regions; a device isolation film defining the active regions; a word line arranged over the active regions and the device isolation film and extending in a first horizontal direction; and a gate dielectric film arranged between the substrate and the word line and between the device isolation film and the word line, in which, in a second horizontal direction orthogonal to the first horizontal direction, a width of a second portion of the word line over the device isolation film is greater than a width of a first portion of the word line over the active regions. To manufacture the integrated circuit device, an impurity region is formed in the substrate and the device isolation film by implanting dopant ions into the substrate and the device isolation film, and a thickness of a portion of the impurity region is reduced.

公开(公告)号：US10886375B2

公开(公告)日：2021-01-05

申请号：US16288910

申请日：2019-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin Lee ,  Junsoo Kim ,  Moonyoung Jeong ,  Satoru Yamada ,  Dongsoo Woo ,  Jiyoung Kim

IPC: H01L29/40 ,  H01L29/423 ,  H01L27/108 ,  H01L21/84 ,  H01L29/775 ,  H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  B82Y10/00 ,  H01L27/088

Abstract: A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.

公开(公告)号：US12279435B2

公开(公告)日：2025-04-15

申请号：US17683460

申请日：2022-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Hyuncheol Kim ,  Jongman Park ,  Dongsoo Woo

IPC: H10B51/20 ,  H10B51/10 ,  H10B51/40

Abstract: A semiconductor device includes first conductive lines provided on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, second conductive lines spaced apart from the first conductive lines in a second direction parallel to the top surface of the substrate, a gate electrode disposed between the first and second conductive lines and extended in the first direction, a plurality of channel patterns provided to enclose a side surface of the gate electrode and spaced apart from each other in the first direction, a ferroelectric pattern between each of the channel patterns and the gate electrode, and a gate insulating pattern between each of the channel patterns and the ferroelectric pattern. Each of the channel patterns is connected to a corresponding one of the first conductive lines and a corresponding one of the second conductive lines.

公开(公告)号：US11862220B2

公开(公告)日：2024-01-02

申请号：US17836228

申请日：2022-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjun Lee ,  Yongseok Kim ,  Hyuncheol Kim ,  Jongman Park ,  Dongsoo Woo ,  Kyunghwan Lee

IPC: G11C11/22 ,  G11C5/06

CPC classification number: G11C11/2273 ,  G11C5/06 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/2275

Abstract: Provided is a memory device. The memory device may include a substrate, a ferroelectric field effect transistor disposed on the substrate, a first channel contacting a gate structure of the ferroelectric field effect transistor and extending in a vertical direction from the gate structure of the ferroelectric field effect transistor, a selection word line disposed at one side of the first channel, a first gate dielectric layer disposed between the first channel and the selection word line, and a cell word line disposed on top of the first channel.