公开(公告)号：US20230038363A1

公开(公告)日：2023-02-09

申请号：US17848844

申请日：2022-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Chu OH ,  Byungchul JANG ,  Junyeong SEOK ,  Younggul SONG ,  Joonsung LIM

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: Provided is a three-dimensional storage device using wafer-to-wafer bonding. A storage device includes a first chip including a first substrate and a peripheral circuit region including a first control logic circuit configured to control operation modes of the non-volatile memory device and a second chip including a second substrate and three-dimensional arrays of non-volatile memory cells. The second chip may be vertically stacked on the first chip so that a first surface of the first substrate faces a first surface of the second substrate, and a second control logic circuit is configured to control operation conditions of the non-volatile memory device and is arranged on a second surface of the second substrate, the second surface of the second substrate being opposite to the first surface of the second substrate of the second chip.

公开(公告)号：US20200211656A1

公开(公告)日：2020-07-02

申请号：US16817043

申请日：2020-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Chu OH ,  Pilsang YOON ,  Jun Jin KONG ,  Jisu KIM ,  Hong Rak SON ,  Jinbae BANG ,  Daeseok BYEON ,  Taehyun SONG ,  Dongjin SHIN ,  Dongsup JIN

IPC: G11C16/28 ,  G11C29/02 ,  G11C16/04 ,  G11C29/50 ,  G11C16/26 ,  G11C16/34 ,  G11C11/56 ,  G11C16/10

Abstract: An method of operating a nonvolatile memory device including a plurality of memory cells comprises receiving a read command from an external device, in response to the read command, performing, based on a reference voltage, a first cell counting operation with respect to the plurality of memory cells, adjusting at least one read voltage of first through nth read voltages (where n is a natural number greater than 1) based on a first result of the first cell counting operation, and performing, based on the adjusted at least one read voltage, a read operation corresponding to the read command with respect to the plurality of memory cells.

公开(公告)号：US20180294036A1

公开(公告)日：2018-10-11

申请号：US16003729

申请日：2018-06-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Chu OH ,  Pilsang YOON ,  Jun Jin KONG ,  Jisu KIM ,  Hong Rak SON ,  Jinbae BANG ,  Daeseok BYEON ,  Taehyun SONG ,  Dongjin SHIN ,  Dongsup JIN

IPC: G11C16/28 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C11/56

CPC classification number: G11C16/28 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/04 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3495 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50004 ,  G11C2029/5004 ,  G11C2211/563 ,  G11C2211/5634

Abstract: An method of operating a nonvolatile memory device including a plurality of memory cells comprises receiving a read command from an external device, in response to the read command, performing, based on a reference voltage, a first cell counting operation with respect to the plurality of memory cells, adjusting at least one read voltage of first through nth read voltages (where n is a natural number greater than 1) based on a first result of the first cell counting operation, and performing, based on the adjusted at least one read voltage, a read operation corresponding to the read command with respect to the plurality of memory cells.

公开(公告)号：US20240311054A1

公开(公告)日：2024-09-19

申请号：US18595769

申请日：2024-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Chu OH ,  Beomkyu SHIN

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0673

Abstract: Provided is a memory device including a plurality of memory blocks including of at least one subblock, wherein the memory block includes a first subblock configured to store first data including of at least one bit, and a second subblock configured to perform an erase operation independently of the first subblock and store second data including of at least one bit. The memory device is configured to perform a read operation on the second data in response to a write operation being performed on the second data in the second subblock. The memory device is configured to perform a write operation on the first data in the first subblock in response to a read operation being performed on the second data in the second subblock.

公开(公告)号：US20240311011A1

公开(公告)日：2024-09-19

申请号：US18674089

申请日：2024-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyeong SEOK ,  Younggul SONG ,  Eun Chu OH ,  Byungchul JANG ,  Joonsung LIM

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/064 ,  G06F3/0679

Abstract: In a method of operating one or more nonvolatile memory devices including one or more memory blocks, each memory block includes a plurality of memory cells and a plurality of pages arranged in a vertical direction. Pages arranged in a first direction of a channel hole are set as first to N-th pages. A size of the channel hole increases in the first direction and decreases in the second direction. Pages arranged in a second direction of the channel hole are set as (N+1)-th to 2N-th pages. First to N-th page pairs are set such that a K-th page among the first to the N-th pages and an (N+K)-th page among the (N+1)-th to 2N-th pages form one page pair. Parity regions of two pages included in at least one page pair are shared by the two pages included in the at least one page pair.

公开(公告)号：US20230207017A1

公开(公告)日：2023-06-29

申请号：US17810894

申请日：2022-07-06

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Eun Chu OH ,  Junyeong SEOK ,  Younggul SONG

IPC: G11C16/10 ,  G11C16/28 ,  G11C16/34 ,  G11C16/08 ,  G11C16/32

CPC classification number: G11C16/102 ,  G11C16/28 ,  G11C16/3495 ,  G11C16/08 ,  G11C16/32

Abstract: A storage device includes a nonvolatile memory device and a storage controller to control operation of the nonvolatile memory device. The storage controller assigns a program operation associated with data to be programmed, to one of a first program operation or a second program operation, controls the nonvolatile memory device to perform the first program operation on first memory blocks and to perform the second program operation on at least one second memory block, and controls the nonvolatile memory to select one of the first program operation on a third memory block in an erase state or the second program operation on the second memory block, and to perform the selected program operation after the first program operation on the first memory blocks is completed.

公开(公告)号：US20230153202A1

公开(公告)日：2023-05-18

申请号：US17965091

申请日：2022-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younggul SONG ,  Byungchul JANG ,  Junyeong SEOK ,  Eun Chu OH

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/0793

Abstract: A method of operating a memory system that comprises a memory device including a plurality of memory blocks and a memory controller, includes detecting a first memory block having a degradation count greater than or equal to a first reference value by the memory controller. A first command for the first memory block is transmitted to the memory device by the memory controller. A first voltage is applied to all of a plurality of word lines connected to the first memory block and a second voltage to a bit line connected to the first memory block in response to the first command by the memory device. The first voltage is greater than a voltage applied to turn on memory cells connected to all of the plurality of word lines. The second voltage is greater than a voltage applied to the bit line during program, read or erase operations.

公开(公告)号：US20210158877A1

公开(公告)日：2021-05-27

申请号：US17168613

申请日：2021-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Jin SHIN ,  Ji Su KIM ,  Dae Seok BYEON ,  Ji Sang LEE ,  Jun Jin KONG ,  Eun Chu OH

IPC: G11C16/26 ,  G11C16/10 ,  G11C5/14 ,  G11C16/24 ,  G11C16/08 ,  G11C16/32 ,  G11C11/56

Abstract: A non-volatile memory device including: a page buffer configured to latch a plurality of page data constituting one bit page of a plurality of bit pages, and a control logic configured to compare results of a plurality of read operations performed in response to a high-priority read signal set to select one of a plurality of read signals included in the high-priority read signal set as a high-priority read signal, and determine a low-priority read signal corresponding to the high-priority read signal, wherein the high-priority read signal set is for reading high-priority page data, and the low-priority read signal is for reading low-priority page data.

公开(公告)号：US20200185030A1

公开(公告)日：2020-06-11

申请号：US16545765

申请日：2019-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Chu OH

IPC: G11C13/00 ,  G06F11/10

Abstract: A memory device includes a memory cell array including a plurality of memory cells and a control logic to control a write operation on the memory cell array. When operating in a first data comparison write (DCW) mode, data is written to first memory cells in which data values are changed, in a first region, data is written to second memory cells in which data values are not changed, and, in a second region, data write is skipped for second memory cells in which data values are not changed.

公开(公告)号：US20200167290A1

公开(公告)日：2020-05-28

申请号：US16446912

申请日：2019-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Chu OH

IPC: G06F12/10 ,  G06F7/58 ,  G11C16/22 ,  G06F12/02 ,  G06F13/16

Abstract: A memory system includes a memory device including a plurality of memory cells, and a memory controller configured to control the memory device. The memory controller includes a random number generator configured to generate a random number based on read data from the memory device, and an address translation module configured to generate a key based on the random number and to translate a first address into a second address by performing a calculation on the first address and the key.