公开(公告)号：US10819381B2

公开(公告)日：2020-10-27

申请号：US16449765

申请日：2019-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangbong Lee ,  Namhyung Kim ,  Taekon Kim ,  Kiyul Lim ,  Jaehoon Lee

IPC: G06F3/02 ,  H04B1/3888 ,  H04M1/02 ,  G06F1/16

Abstract: An electronic device according to certain embodiments includes a housing, a first glass plate coupled to the housing and defining an inner space, the first glass plate including a peripheral portion including: a first, second, third, fourth, and fifth surface forming an edge of the glass plate, the first and fifth surfaces being substantially parallel and the third surface being substantially perpendicular to the first and fifth surfaces, a decorative layer formed of a first material, disposed on a first area of the fifth surface such that a second area disposed between the fourth surface and the first area is uncovered by the decorative layer, and a protective layer formed of a second material, covering the second surface, the third surface, the fourth surface, the second area of the fifth surface, and a part of the decorative layer.

公开(公告)号：US20240355735A1

公开(公告)日：2024-10-24

申请号：US18419856

申请日：2024-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyemi LEE ,  Seungyoon Kim ,  Heesuk Kim ,  Sangjae Lee ,  Jaehoon Lee ,  Juyoung Lim ,  Minkyu Chung ,  Sanghun Chun ,  Jeehoon Han

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: A semiconductor device includes a plate layer, gate electrodes and interlayer insulating layers alternately stacked on the plate layer in a first direction perpendicular to an upper surface of the plate layer and forming a first stack structure and a second stack structure on the first stack structure, a channel structure penetrating through the gate electrodes and extending in the first direction, and a contact plug extending in the first direction and electrically connected to one of the gate electrodes, wherein the second stack structure includes a first gate electrode on a lowermost portion, a first interlayer insulating layer on the first gate electrode, and a second interlayer insulating layer on the first interlayer insulating layer, and the first interlayer insulating layer has a first thickness, and the second interlayer insulating layer has a second thickness smaller than the first thickness.

公开(公告)号：US11899959B2

公开(公告)日：2024-02-13

申请号：US17337992

申请日：2021-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaewon Park ,  Sangkil Park ,  Jaehoon Lee

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0614 ,  G06F3/0679

Abstract: A method of testing a memory device, a memory built-in self-test (MBIST) circuit, and a memory device for improving reliability and reducing a test time. The memory device includes a plurality of memory banks and the MBIST circuit. The MBIST circuit is configured to generate double data rate (DDR) test patterns and parallel bit test (PBT) test patterns to test the memory banks. When a defective cell is detected as a result of the PBT test or the DDR test, the MBIST circuit is configured to perform a repair operation for replacing the defective cell with a redundancy cell and perform a re-test to verify the repair operation. The MBIST circuit may be configured to perform the DDR test on one or more memory cells including the defective cell during the re-test.

公开(公告)号：US11233062B2

公开(公告)日：2022-01-25

申请号：US16827778

申请日：2020-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihye Kim ,  Jaehoon Lee ,  Jiyoung Kim ,  Bongtae Park ,  Jaejoo Shim

IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/112 ,  H01L27/11585 ,  H01L27/32 ,  H01L29/49

Abstract: A semiconductor device includes a substrate having a conductive region and an insulating region; gate electrodes including sub-gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate and extending in a second direction perpendicular to the first direction and gate connectors connecting the sub-gate electrodes disposed on the same level; channel structures penetrating through the gate electrodes and extending in the conductive region of the substrate; and a first dummy channel structure penetrating through the gate electrodes and extending in the insulating region of the substrate and disposed adjacent to at least one side of the gate connectors in a third direction perpendicular to the first and second directions.

公开(公告)号：US11811364B2

公开(公告)日：2023-11-07

申请号：US17845378

申请日：2022-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehong Jung ,  Seunghyun Oh ,  Jinhyeon Lee ,  Gihyeok Ha ,  Seungjin Kim ,  Joomyoung Kim ,  Yelim Youn ,  Jaehoon Lee

IPC: H03B5/32 ,  G06F1/06 ,  H03B5/04 ,  H03B5/20

CPC classification number: H03B5/32 ,  G06F1/06 ,  H03B5/04 ,  H03B5/20 ,  H03B2200/0082

Abstract: A clock integrated circuit is provided. The clock integrated circuit includes: a first clock generator which includes a crystal oscillator configured to generate a first clock signal; and a second clock generator which includes a resistance-capacitance (RC) oscillator and a first frequency divider, and is configured to: generate a second clock signal using the first frequency divider based on a clock signal output from the RC oscillator; perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider to a first frequency division ratio based on the first clock signal; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.

公开(公告)号：US11637110B2

公开(公告)日：2023-04-25

申请号：US17580811

申请日：2022-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihye Kim ,  Jaehoon Lee ,  Jiyoung Kim ,  Bongtae Park ,  Jaejoo Shim

IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/112 ,  H01L27/11585 ,  H01L27/32 ,  H01L29/49

Abstract: A semiconductor device includes a substrate having a conductive region and an insulating region; gate electrodes including sub-gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate and extending in a second direction perpendicular to the first direction and gate connectors connecting the sub-gate electrodes disposed on the same level; channel structures penetrating through the gate electrodes and extending in the conductive region of the substrate; and a first dummy channel structure penetrating through the gate electrodes and extending in the insulating region of the substrate and disposed adjacent to at least one side of the gate connectors in a third direction perpendicular to the first and second directions.

公开(公告)号：US11509298B2

公开(公告)日：2022-11-22

申请号：US17514552

申请日：2021-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehoon Lee ,  Yong Lim ,  Wan Kim ,  Barosaim Sung ,  Seunghyun Oh

IPC: H03K5/22 ,  H03K5/24 ,  H03M1/10

Abstract: A comparator configured to calibrate an offset according to a control signal, including an input circuit configured to receive a first input signal and a second input signal, and to generate a first internal signal corresponding to the first input signal and a second internal signal corresponding to the second input signal; a differential amplification circuit configured to consume a supply current flowing from a positive voltage node having a positive supply voltage to a negative voltage node having a negative supply voltage, and to generate an output signal by amplifying a difference between the first internal signal and the second internal signal; and a current valve configured to adjust at least a portion of the supply current based on the control signal.

公开(公告)号：US11405963B2

公开(公告)日：2022-08-02

申请号：US16863141

申请日：2020-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyeok Lee ,  Taikuin Mun ,  Wonjung Lee ,  Jaehoon Lee

IPC: H04W76/10 ,  H04W76/30 ,  H04M1/72448

Abstract: An electronic device provided. The electronic device comprises at least one communication circuit configured to perform communication with at least one external device, at least one processor operatively connected with the at least one communication circuit, and a memory operatively connected with the at least one processor, wherein the memory stores instructions to, when executed, enable the at least one processor to control the at least one communication circuit to establish a first communication connection with a first wearable device, control the at least one communication circuit to receive a signal for establishing a second communication connection from a second wearable device, the signal including information indicating whether a user wears the second wearable device, identify whether the user wears the second wearable device based on the information, and based on identifying that the user wears the second wearable device, control the at least one communication circuit to release the first communication connection and establish the second communication connection with the second wearable device. Other various embodiments are possible as well.

公开(公告)号：US10992489B2

公开(公告)日：2021-04-27

申请号：US16535683

申请日：2019-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyeok Lee ,  Taikuin Mun ,  Jaehoon Lee ,  Jongkeun Choi

IPC: H04M11/04 ,  H04L12/18 ,  H04L12/28 ,  H04L12/58

Abstract: An electronic device includes a display, communication circuitry performing wireless connection with an external electronic device, a processor operatively coupled with the display and the communication circuitry, and a memory operatively connected with the processor. Based on executing instructions stored in the memory, the processor is configured to control the electronic device to receive information on a first notification message generated within the external electronic device using the communication circuitry. Based on instructions stored in the memory being executed, the processor controls the electronic device to display the first notification message through the display. Based on the instructions stored in the memory being executed, the processor is configured to control the electronic device to receive one or more second notification messages which have been generated within the external electronic device prior to the first notification message. Based on instructions stored in the memory being executed, the processor is configured to control the electronic device to display, in response to an input, the second notification message in at least a portion of the display.

公开(公告)号：US09954052B2

公开(公告)日：2018-04-24

申请号：US14958146

申请日：2015-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehoon Lee

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L21/8238

CPC classification number: H01L29/0615 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/1054 ,  H01L29/16

Abstract: A semiconductor device is provided as follows. A substrate includes an NMOS region and a PMOS region. A first trench and a second trench are disposed in the NMOS region. A first buffer layer is disposed in the first trench and the second trench. A stressor is disposed in the first trench and the second trench and disposed on the first buffer layer. A first channel region is disposed between the first trench and the second trench and disposed in the substrate. A first gate electrode is disposed on the first channel area. A third trench is disposed in the PMOS region. A second buffer layer is disposed in the third trench. A second channel area is disposed in the third trench, disposed on the second buffer layer, and has a different semiconductor layer from the substrate. A second gate electrode is disposed on the second channel area.