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    Electronic apparatus and operating method thereof
    11.
    发明授权
    Electronic apparatus and operating method thereof 有权

    公开(公告)号：US10171949B2

    公开(公告)日：2019-01-01

    申请号：US15482123

    申请日：2017-04-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Choonkyoung Moon ,  Jangwoo Lee ,  Ja Ok Koo ,  Hyunsoo Nah ,  Eunkyung Yoo

    IPC: H04W64/00 ,  H04W4/029 ,  H04L12/28 ,  H04L29/08

    Abstract: The present disclosure relates to an electronic device and an operating method thereof. The electronic device includes a memory configured to store at least one expected movement path, and a processor configured to confirm a first location of a user, predict a second location on a basis of the first location and a pre-stored at least one expected movement path, and provide an information service providing signal to at least one external device present in the second location. The method includes confirming a first location of a user, predicting a second location on a basis of the first location and a pre-stored at least one expected movement path, and providing an information service providing signal to at least one external device present in the second location.

    Semiconductor packages having a dam structure
    12.
    发明授权
    Semiconductor packages having a dam structure 有权

    公开(公告)号：US12261093B2

    公开(公告)日：2025-03-25

    申请号：US17883726

    申请日：2022-08-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongho Kim ,  Jongbo Shim ,  Hwanpil Park ,  Jangwoo Lee

    IPC: H01L23/31 ,  H01L23/00 ,  H01L25/065

    Abstract: A semiconductor package is disclosed. The disclosed semiconductor package includes a substrate having bonding pads at an upper surface thereof, a lower semiconductor chip, at least one upper semiconductor chip disposed on the lower semiconductor chip, and a dam structure having a closed loop shape surrounding the lower semiconductor chip. The dam structure includes narrow and wide dams disposed between the lower semiconductor chip and the bonding pads. The wide dam has a greater inner width than the narrow dam. The semiconductor packages further includes an underfill disposed inside the dam structure and being filled between the substrate and the lower semiconductor chip.

    Interface circuit, memory device, storage device, and method of operating the memory device
    14.
    发明授权
    Interface circuit, memory device, storage device, and method of operating the memory device 有权

    公开(公告)号：US11960728B2

    公开(公告)日：2024-04-16

    申请号：US17536506

    申请日：2021-11-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Daehoon Na ,  Jangwoo Lee ,  Jeongdon Ihm

    IPC: G06F3/06

    CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0679

    Abstract: An interface circuit of a memory device including a plurality of memory dies including a plurality of registers corresponding to the plurality of memory dies, respectively, the plurality of registers each configured to store command information related to a data operation command, a demultiplexer circuit configured to provide input command information to a selected register from among the plurality of registers according to at least one of a first address or a first chip selection signal, the input command information being received from outside the interface circuit, and a multiplexer circuit configured to receive output command information from the selected register from among the plurality of registers and output the output command information according to at least one of a second address or a second chip selection signal may be provided.

    INTERFACE CHIP USED TO SELECT MEMORY CHIP AND STORAGE DEVICE INCLUDING INTERFACE CHIP AND MEMORY CHIP
    18.
    发明申请
    INTERFACE CHIP USED TO SELECT MEMORY CHIP AND STORAGE DEVICE INCLUDING INTERFACE CHIP AND MEMORY CHIP 审中-公开

    公开(公告)号：US20200167298A1

    公开(公告)日：2020-05-28

    申请号：US16425105

    申请日：2019-05-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Manjae Yang ,  Jangwoo Lee ,  Hwasuk Cho ,  Jeongdon Ihm

    IPC: G06F13/16 ,  G06F3/06 ,  G11C7/10

    Abstract: An interface chip includes a command decoder configured to decode a command included in data input/output signals based on a clock signal, clock masking circuitry configured to generate a masking clock signal including an edge corresponding to a first edge among first to n-th edges of the clock signal (n being an integer of 2 or more), clock latency circuity configured to transmit, to an external chip, a latency clock signal including edges corresponding to the second to n-th edges of the clock signal, chip select circuitry configured to generate a chip select signal based on an address included in the data input/output signals and the masking clock signal, and chip enable control circuitry configured to receive a chip enable signal indicating a channel for the data input/output signals and transmit the chip enable signal to the external chip based on the chip select signal.

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