公开(公告)号：US10593652B2

公开(公告)日：2020-03-17

申请号：US16448392

申请日：2019-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heung-Kyu Kwon ,  Min-Ok Na ,  Sung-Woo Park ,  Ji-Hyun Park ,  Su-Min Park

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L23/00 ,  H01L25/10 ,  H01L25/18 ,  H01L25/00 ,  H01L23/48

Abstract: An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.

公开(公告)号：US10431522B2

公开(公告)日：2019-10-01

申请号：US15856800

申请日：2017-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Ok Na ,  Jongkook Kim ,  Hyo-Chang Ryu ,  Jin-woo Park ,  BongJin Son ,  Jangwoo Lee

IPC: H01L23/373 ,  H01L23/367 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/50 ,  H01L23/00

Abstract: Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.

公开(公告)号：US10403606B2

公开(公告)日：2019-09-03

申请号：US15971600

申请日：2018-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heung-Kyu Kwon ,  Min-Ok Na ,  Sung-Woo Park ,  Ji-Hyun Park ,  Su-Min Park

IPC: H01L25/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L23/00 ,  H01L25/10 ,  H01L25/18 ,  H01L23/48

Abstract: A method for fabricating a semiconductor package including mounting a first semiconductor chip on a first substrate, disposing a first connector on the first substrate, placing a molding control film on the first semiconductor chip to horizontally extend over the first substrate, filling a space between the molding control film and the first substrate with a molding compound such that the molding compound contacts side surfaces of the first semiconductor chip and covers the first connector and does not cover a top surface of the first semiconductor chip, detaching the molding control film, forming an opening through the molding compound to expose a portion of the first connector, disposing a second connector and a second semiconductor chip on opposite surfaces of a second substrate, respectively, and placing the second substrate on the first substrate such that the second connector contacts the first connector may be provided.

公开(公告)号：US08829686B2

公开(公告)日：2014-09-09

申请号：US13678205

申请日：2012-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Sun Hong ,  Young-Min Kim ,  Jung-Woo Kim ,  Min-Ok Na ,  Hyo-Chang Ryu ,  Jong-Bo Shim

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/29 ,  H01L23/498 ,  H01L25/10 ,  H01L23/31

CPC classification number: H01L23/498 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A package-on-package assembly includes first and second packages and an adhesion member positioned between the first and second packages and adhering the first and second packages to one another. The first package may include a first substrate having a first surface and a second surface facing each other and including a land pad formed on the first surface, a first semiconductor chip formed on the first surface, and a first encapsulant member encapsulating the first surface and the first semiconductor chip and including a through-via spaced apart from the first semiconductor chip and exposing the land pad and a trench formed between the first semiconductor chip and the through-via, and wherein at least a portion of the trench is filled with adhesion member material.

Abstract translation: 包装包装组件包括第一和第二包装以及定位在第一和第二包装之间并将第一和第二包装彼此粘合的粘合部件。 第一封装可以包括具有第一表面和第二表面的第一衬底，第一表面和第二表面彼此面对并且包括形成在第一表面上的焊盘焊盘，形成在第一表面上的第一半导体芯片和封装第一表面的第一密封剂构件， 所述第一半导体芯片并且包括与所述第一半导体芯片间隔开的通孔，并且暴露所述焊盘焊盘和形成在所述第一半导体芯片和所述通孔之间的沟槽，并且其中所述沟槽的至少一部分填充有粘附 会员资料

公开(公告)号：US20130187288A1

公开(公告)日：2013-07-25

申请号：US13678205

申请日：2012-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Sun Hong ,  Young-Min Kim ,  Jung-Woo Kim ,  Min-Ok Na ,  Hyo-Chang Ryu ,  Jong-Bo Shim

IPC: H01L23/498

CPC classification number: H01L23/498 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A package-on-package assembly includes first and second packages and an adhesion member positioned between the first and second packages and adhering the first and second packages to one another. The first package may include a first substrate having a first surface and a second surface facing each other and including a land pad formed on the first surface, a first semiconductor chip formed on the first surface, and a first encapsulant member encapsulating the first surface and the first semiconductor chip and including a through-via spaced apart from the first semiconductor chip and exposing the land pad and a trench formed between the first semiconductor chip and the through-via, and wherein at least a portion of the trench is filled with adhesion member material.

Abstract translation: 包装包装组件包括第一和第二包装以及定位在第一和第二包装之间并将第一和第二包装彼此粘合的粘合部件。 第一封装可以包括具有第一表面和第二表面的第一衬底，第一表面和第二表面彼此面对并且包括形成在第一表面上的焊盘焊盘，形成在第一表面上的第一半导体芯片和封装第一表面的第一密封剂构件， 所述第一半导体芯片并且包括与所述第一半导体芯片间隔开的通孔，并且暴露所述焊盘焊盘和形成在所述第一半导体芯片和所述通孔之间的沟槽，并且其中所述沟槽的至少一部分填充有粘附 会员资料

公开(公告)号：US20200006188A1

公开(公告)日：2020-01-02

申请号：US16566380

申请日：2019-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Ok Na ,  Jongkook Kim ,  Hyo-Chang Ryu ,  Jin-woo Park ,  BongJin Son ,  Jangwoo Lee

IPC: H01L23/373 ,  H01L23/367 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L25/065

Abstract: Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.

公开(公告)号：US10950521B2

公开(公告)日：2021-03-16

申请号：US16566380

申请日：2019-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Ok Na ,  Jongkook Kim ,  Hyo-Chang Ryu ,  Jin-woo Park ,  BongJin Son ,  Jangwoo Lee

IPC: H01L23/373 ,  H01L23/367 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/50 ,  H01L23/00

Abstract: Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.

公开(公告)号：US09978721B2

公开(公告)日：2018-05-22

申请号：US15241452

申请日：2016-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heung-Kyu Kwon ,  Min-Ok Na ,  Sung-Woo Park ,  Ji-Hyun Park ,  Su-Min Park

IPC: H05K1/11 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/552 ,  H01L23/00 ,  H01L25/10 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/565 ,  H01L21/566 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16112 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/49 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01064 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.

公开(公告)号：US09214484B2

公开(公告)日：2015-12-15

申请号：US14450864

申请日：2014-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ok-Gyeong Park ,  Min-Ok Na

IPC: H01L23/28 ,  H01L27/146

CPC classification number: H01L27/14618 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/00011

Abstract: An image sensor package may include: a package substrate including a chip attachment area on an upper surface thereof, a pad area having a plurality of pads around the chip attachment area, and a holder attachment area at an outside of the pad area, wherein an upper surface of the holder attachment area is at a lower level than an upper surface of the pad area; an image sensor chip mounted on the chip attachment area of the package substrate; a transparent member above the package substrate and configured to cover the image sensor chip; and a holder on the holder attachment area of the package substrate and configured to fix the transparent member.

Abstract translation: 图像传感器封装可以包括：封装基板，其包括在其上表面上的芯片附接区域，具有围绕芯片附接区域的多个焊盘的焊盘区域以及焊盘区域的外部的保持器附接区域，其中 保持器附接区域的上表面处于比焊盘区域的上表面更低的水平面上; 安装在封装基板的芯片安装区域上的图像传感器芯片; 透明构件，其在所述封装基板上方并且被构造成覆盖所述图像传感器芯片; 以及在所述封装基板的所述保持器附着区域上的保持器，并且被配置为固定所述透明构件。

公开(公告)号：US09040351B2

公开(公告)日：2015-05-26

申请号：US14339563

申请日：2014-07-24

Applicant: Samsung Electronics Co., Ltd

Inventor： Heung-Kyu Kwon ,  Jae-Wook Yoo ,  Hyon-Chol Kim ,  Su-Chang Lee ,  Min-Ok Na

IPC: H01L23/52 ,  H01L25/00 ,  H01L23/373 ,  H01L23/498 ,  H01L25/10 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/565 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3128 ,  H01L23/3737 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16221 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83097 ,  H01L2224/83191 ,  H01L2225/06503 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/0401

Abstract: A stack package includes a lower package including a lower package substrate and a lower semiconductor chip disposed on the lower package substrate, an upper package including an upper package substrate and an upper semiconductor chip disposed on the upper package substrate, a fastening element formed between a top surface of the lower semiconductor chip and a bottom surface of the upper package substrate, and a halogen-free inter-package connector connecting the lower package substrate to the upper package substrate.

Abstract translation: 堆叠封装包括下封装，其包括下封装基板和设置在下封装基板上的下半导体芯片，上封装，包括上封装基板和布置在上封装基板上的上半导体芯片，形成在下封装基板上的紧固元件 下部半导体芯片的上表面和上部封装基板的底面，以及将下部封装基板连接到上部封装基板的无卤素的封装间连接器。