公开(公告)号：US20250071993A1

公开(公告)日：2025-02-27

申请号：US18605147

申请日：2024-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunji Kim ,  Sehee Jang ,  Jeehoon Han

IPC: H10B43/27 ,  H10B41/27

Abstract: The present disclosure relates to three-dimensional (3D) semiconductor memory devices and electronic systems. An example 3D semiconductor memory device comprises a substrate that includes a cell array region and a connection region, a structure in which a plurality of dielectric layers and a plurality of gate electrodes are alternately stacked on the substrate, a plurality of dummy vertical structures that extend through the structure on the connection region, and a gate contact that extends through the structure on the connection region and is connected to one gate electrode of the plurality of gate electrodes. The gate contact is between the plurality of dummy vertical structures in a plan view. The gate contact includes a first portion and a plurality of second portions that extend between the plurality of dummy vertical structures.

公开(公告)号：US20250056805A1

公开(公告)日：2025-02-13

申请号：US18932884

申请日：2024-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kanamori Kohji ,  Jeehoon Han

IPC: H10B43/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/48 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: Disclosed are three-dimensional semiconductor memory devices, methods of manufacturing the same, and electronic systems including the same. The device includes a peripheral circuit structure on a substrate, and a cell array structure including a stack structure that includes gate electrodes on the peripheral circuit structure, a first source conductive pattern on the stack structure, and vertical channel structures in vertical channel holes that penetrate the stack structure and the first source conductive pattern. The vertical channel structure includes a data storage pattern on a sidewall of the vertical channel hole, a vertical semiconductor pattern on the data storage pattern, and a second source conductive pattern on the vertical semiconductor pattern and surrounded by the data storage pattern. A thickness of the data storage pattern between the first source conductive pattern and the second source conductive pattern is greater than it is between the stack structure and the vertical semiconductor pattern.

公开(公告)号：US20240324233A1

公开(公告)日：2024-09-26

申请号：US18598414

申请日：2024-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyeonghoon Park ,  Jaebok Baek ,  Janggn Yun ,  Jeehoon Han

IPC: H10B43/40 ,  G11C16/04 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/40 ,  G11C16/0483 ,  H01L23/5283 ,  H01L25/0657 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: A non-volatile memory device includes a peripheral circuit structure and a cell array structure on the peripheral circuit structure, where the cell array structure includes a base insulation layer, a common source line layer on the base insulation layer, a buffer insulation layer on the common source line layer, and a cell stack on the buffer insulation layer, where the cell stack includes a plurality of gate electrodes and a plurality of insulation layers, where the plurality of gate electrodes have a staircase shape, a plurality of gate contact plugs that extend into the cell stack, and a plurality of protection structures between the plurality of gate contact plugs and the base insulation layer.

公开(公告)号：US11968836B2

公开(公告)日：2024-04-23

申请号：US17838644

申请日：2022-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan Son ,  Jeehoon Han

IPC: H01L29/417 ,  H01L29/423 ,  H10B41/20 ,  H10B43/20 ,  H10B43/27 ,  H10B43/30 ,  H10B51/20 ,  H10K19/00

CPC classification number: H10B43/27 ,  H01L29/41741 ,  H01L29/42344 ,  H10B41/20 ,  H10B43/20 ,  H10B43/30 ,  H10B51/20 ,  H10K19/201

Abstract: Three-dimensional (3D) semiconductor memory devices are provided. A 3D semiconductor memory device includes an electrode structure on a substrate. The electrode structure includes gate electrodes stacked on the substrate. The gate electrodes include electrode pad regions. The 3D semiconductor memory device includes a dummy vertical structure penetrating one of the electrode pad regions. The dummy vertical structure includes a dummy vertical semiconductor pattern and a contact pattern extending from a portion of the dummy vertical semiconductor pattern toward the substrate.

公开(公告)号：US20240014134A1

公开(公告)日：2024-01-11

申请号：US18370913

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungyoon Kim ,  Jeongyong Sung ,  Sanghun Chun ,  Jihwan Kim ,  Sunghee Chung ,  Jeehoon Han

IPC: H01L23/528 ,  H10B43/40 ,  H01L23/522 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L25/065

CPC classification number: H01L23/5283 ,  H10B43/40 ,  H01L23/5226 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L25/0652 ,  H01L2225/06506

Abstract: A semiconductor device includes a pattern structure; a stack structure including gate layers stacked in a first region on the pattern structure and extending into a second region; a memory vertical structure penetrating the stack structure in the first region; gate contact plugs electrically connected to the gate layers in the second region; and a first peripheral contact plug spaced apart from the gate layers, the gate layers including a first gate layer, the gate contact plugs including a first gate contact plug electrically connected to the first gate layer, side surfaces of the first gate contact plug and the first peripheral contact plug having different numbers of upper bending portions, and the number of upper bending portions of the side surface of the first gate contact plug being greater than the number of upper bending portions of the side surface of the first peripheral contact plug.

公开(公告)号：US11856770B2

公开(公告)日：2023-12-26

申请号：US17357213

申请日：2021-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangyoung Jung ,  Jaebok Baek ,  Giyong Chung ,  Jeehoon Han

IPC: H10B43/10 ,  H01L25/18 ,  H01L25/065 ,  H10B43/27 ,  H01L23/00

CPC classification number: H10B43/10 ,  H01L25/0657 ,  H01L25/18 ,  H10B43/27 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor device includes a gate electrode structure, a channel, first division patterns, and a second division pattern. The gate electrode structure is on a substrate, and includes gate electrodes stacked in a first direction perpendicular to the substrate. Each gate electrode extends in a second direction parallel to the substrate. The channel extends in the first direction through the gate electrode structure. The first division patterns are spaced apart from each other in the second direction, and each first division pattern extends in the second direction through the gate electrode structure. The second division pattern is between the first division patterns, and the second division pattern and the first division patterns together divide a first gate electrode in a third direction parallel to the substrate and crossing the second direction. The second division pattern has an outer contour that is a curve in a plan view.

公开(公告)号：US20230380164A1

公开(公告)日：2023-11-23

申请号：US18116434

申请日：2023-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyeonghoon Park ,  Inhwan Baek ,  Jaebok Baek ,  Jeehoon Han ,  Seungyoon Kim ,  Heesuk Kim ,  Byoungjae Park ,  Jongseon Ahn ,  Jumi Yun

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A semiconductor memory device includes: a first semiconductor structure including a first substrate, circuit devices on the first substrate, and a lower interconnection structure connected to the circuit devices; and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure may include: a second substrate having a first region and a second region; a substrate insulating layer extending through the second substrate; a landing pad extending through the substrate insulating layer; gate electrodes, each having a gate pad region on the second region having an exposed upper surface; and a gate contact plug extending through the gate pad region of at least one of the gate electrodes and into the landing pad. The landing pad may include a pad portion that is surrounded by an internal side surface of the substrate insulating layer, and a via portion extending from the pad portion to the lower interconnection structure.

公开(公告)号：US11729972B2

公开(公告)日：2023-08-15

申请号：US16844429

申请日：2020-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan Son ,  Seogoo Kang ,  Jeehoon Han

IPC: H10B43/27 ,  G11C8/14 ,  G11C7/18 ,  H01L29/423 ,  H01L29/792 ,  H10B43/10 ,  H01L21/28

CPC classification number: H10B43/27 ,  G11C7/18 ,  G11C8/14 ,  H01L29/4234 ,  H01L29/7926 ,  H10B43/10 ,  H01L29/40117

Abstract: A semiconductor device is disclosed. The semiconductor device includes a channel structure on a substrate and extending in a first direction perpendicular to a top surface of the substrate; a plurality of gate electrodes on the substrate and spaced apart from one another in the first direction on a sidewall of the channel structure; and a gate insulating layer between each of the plurality of gate electrodes and the channel structure, wherein the channel structure includes a body gate layer extending in the first direction; a charge storage structure surrounding a sidewall of the body gate layer; and a channel layer surrounding sidewall of the charge storage structure.

公开(公告)号：US20230134878A1

公开(公告)日：2023-05-04

申请号：US17842878

申请日：2022-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Yoon Kim ,  Kanamori Kohji ,  Jeehoon Han

IPC: H01L27/11575 ,  H01L23/535 ,  H01L27/11582 ,  H01L27/11573

Abstract: A three-dimensional semiconductor memory device includes a substrate, and a stack structure on the substrate. The stack structure includes first blocks that extend in a first direction and are arranged in a second direction intersecting the first direction, and a second block that is between the first blocks; separation structures that extend in the first direction and are arranged in the second direction between the first blocks and between the first and second blocks; vertical channel structures that penetrate the first blocks and contact the substrate; and through-via structures that penetrate the second block and the substrate. A width of each of the first blocks in the second direction is equal to a width of the second block in the second direction.

公开(公告)号：US11552098B2

公开(公告)日：2023-01-10

申请号：US16885499

申请日：2020-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan Son ,  Sanghoon Jeong ,  Sangjun Hong ,  Seogoo Kang ,  Jeehoon Han

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

Abstract: A semiconductor device includes a lower structure; a stack structure including gate layers and interlayer insulating layers and having an opening; a vertical structure in the opening; a contact structure on the vertical structure; and a conductive line on the contact structure. The vertical structure includes an insulating core region, a channel semiconductor layer covering side and lower surfaces of the insulating core region, data storage patterns between the channel semiconductor layer and the gate layers and spaced apart from each other, a first dielectric layer, and a second dielectric layer. At least a portion of the first dielectric layer is between the data storage patterns and the gate layers, at least a portion of the second dielectric layer is between the data storage patterns and the channel semiconductor layer, and the insulating core region includes first convex portions having increased widths in regions facing the gate layers.