公开(公告)号：US20230297752A1

公开(公告)日：2023-09-21

申请号：US18162120

申请日：2023-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungho Do ,  Jisu Yu ,  Hyeongyu You ,  Minjae Jeong ,  Sanghoon Baek

IPC: G06F30/392

CPC classification number: G06F30/392

Abstract: Integrated circuits including abutted blocks and methods of designing layouts of the integrated circuits are disclosed. The integrated circuit includes a first block having a first function cell array therein, which is at least partially surrounded by a first plurality of finishing cells, and a second block extending adjacent the first block. The second block includes a second function cell array therein, which is at least partially surrounded by a second plurality of finishing cells. The first plurality of finishing cells include: (i) a first finishing cell placed at a boundary of the integrated circuit, and (ii) a second finishing cell different from the first finishing cell, which is placed at a boundary between the first block and the second block.

公开(公告)号：US20230049882A1

公开(公告)日：2023-02-16

申请号：US17818080

申请日：2022-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungho Do ,  Jisu Yu ,  Hyeongyu You ,  Minjae Jeong ,  Yujin Pyo

IPC: G06F30/392 ,  G06F30/394

Abstract: An integrated circuit includes a plurality of standard cells including first and second standard cells arranged adjacent to each other in a first direction, and first, second, and third metal layers sequentially stacked in a vertical direction. At least one power segment is arranged adjacent a region where at least one of the first standard cell and the second standard cell is arranged. The at least one power segment is configured to provide power to the plurality of standard cells and is formed as a pattern of the third metal layer extending in a second direction.

公开(公告)号：US11183233B2

公开(公告)日：2021-11-23

申请号：US16566002

申请日：2019-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop Baeck ,  Tae-Hyung Kim ,  Daeyoung Moon ,  Dong-Wook Seo ,  Inhak Lee ,  Hyunsu Choi ,  Taejoong Song ,  Jae-Seung Choi ,  Jung-Myung Kang ,  Hoon Kim ,  Jisu Yu ,  Sun-Yung Jang

IPC: G11C11/419 ,  G11C7/08 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

公开(公告)号：US20210143144A1

公开(公告)日：2021-05-13

申请号：US17154282

申请日：2021-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho Do ,  Woojin Rim ,  Jisu Yu ,  Jonghoon Jung

IPC: H01L27/02 ,  H01L23/528 ,  G03F1/36 ,  H01L23/522 ,  H01L27/118 ,  H01L21/8238 ,  H01L23/485 ,  H01L27/092 ,  G06F30/398

Abstract: A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.

公开(公告)号：US10332870B2

公开(公告)日：2019-06-25

申请号：US15870143

申请日：2018-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho Do ,  Woojin Rim ,  Jisu Yu ,  Jonghoon Jung

IPC: H01L27/02 ,  H01L27/092 ,  H01L23/522 ,  G06F17/50 ,  G03F1/36 ,  H01L23/528 ,  H01L21/8238 ,  H01L23/485 ,  H01L27/118

Abstract: A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.

公开(公告)号：US12199040B2

公开(公告)日：2025-01-14

申请号：US17180491

申请日：2021-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeongyu You ,  Jisu Yu ,  Jae-Woo Seo ,  Seung Man Lim

IPC: H01L23/528 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Disclosed is a semiconductor device comprising a first logic cell and a second logic cell on a substrate. Each of the first and second logic cells includes a first active region and a second active region that are adjacent to each other in a first direction, a gate electrode that runs across the first and second active regions and extends lengthwise in the first direction, and a first metal layer on the gate electrode. The first metal layer includes a first power line and a second power line that extend lengthwise in a second direction perpendicular to the first direction, and are parallel to each other. The first and second logic cells are adjacent to each other in the second direction along the first and second power lines. The first and second active regions extend lengthwise in the second direction from the first logic cell to the second logic cell.

公开(公告)号：US12147751B2

公开(公告)日：2024-11-19

申请号：US17360355

申请日：2021-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungman Lim ,  Hakchul Jung ,  Sanghoon Baek ,  Jaewoo Seo ,  Jisu Yu ,  Hyeongyu You

IPC: G06F30/3953 ,  G06F30/327 ,  G06F119/06 ,  H01L23/528

Abstract: An integrated circuit includes a plurality of logic cells arranged in a first row extending in a first direction and including different types of active areas extending in the first direction, a filler cell arranged in a second row adjacent to the first row in a second direction orthogonal to the first direction and extending in the first direction, and a first routing wiring line arranged in the second row and connecting a first logic cell and a second logic cell apart from each other by a first distance among the plurality of logic cells. A height of the first row is different from a height of the second row.

公开(公告)号：US20240303410A1

公开(公告)日：2024-09-12

申请号：US18670009

申请日：2024-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jisu Yu ,  Jaeho Park ,  Sanghoon Baek ,  Hyeongyu You ,  Seungyoung Lee ,  Seungman Lim

IPC: G06F30/392 ,  G06F30/3953 ,  G06F30/398 ,  G06F117/12 ,  H01L23/528 ,  H01L29/423

CPC classification number: G06F30/392 ,  G06F30/3953 ,  G06F30/398 ,  H01L23/5283 ,  H01L23/5286 ,  H01L29/42376 ,  G06F2117/12

Abstract: A method includes placing standard cells based on a standard cell library and generating layout data, and placing a filler cell selected from among a first type filler cell and a second type filler cell by using the layout data. The filler cell is placed based on a density of a pattern formed in the standard cell. The standard cell library includes data defining the first and second type filler cells. A density of a contact formed on an active region of the second type filler cell to contact the active region of the second type filler cell is lower than a density of a contact formed on an active region of a first type filler cell to contact the active region of the first type filler cell.

公开(公告)号：US20230290784A1

公开(公告)日：2023-09-14

申请号：US18175696

申请日：2023-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungho Do ,  Jisu Yu ,  Hyeongyu You ,  Yunkyeong Jang ,  Minjae Jeong

IPC: H01L27/118 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L2027/11809

Abstract: An integrated circuit may include a first active pattern group extending in a first direction in a first row and including a plurality of first active patterns overlapping each other in the first direction, the first row extending in the first direction, and a plurality of gate electrodes extending in a second direction perpendicular to the first direction in the first row. The plurality of first active patterns may include any two first active patterns that are adjacent to each other in the first direction, the two first active patterns have first and second widths in the second direction, respectively, and the first and second widths are identical or are different by a first offset or a second offset.

公开(公告)号：US20230086367A1

公开(公告)日：2023-03-23

申请号：US17731464

申请日：2022-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisu Yu ,  Youngsook Do ,  Eunsung Seo ,  Wooseok Kim ,  Wonsik Yu ,  Chanyoung Jeong

IPC: H01L23/528 ,  H01L23/522

Abstract: A semiconductor device includes: a standard cell array including a plurality of standard cells, each of the plurality of standard cells; a plurality of power supply lines configured to provide a power supply voltage and extending in a first direction; a capacitor structure including electrode structures included in each of a plurality of dielectric layers formed on the standard cell array, the capacitor structure having vias connecting the electrode structures; and contacts electrically connecting the capacitor structure and the standard cell array to each other. Each of the plurality of standard cells provides a unit capacitor circuit having capacitance that is based on a connection structure of active regions and gates of first and second transistors thereof.