公开(公告)号：US09986082B2

公开(公告)日：2018-05-29

申请号：US15011227

申请日：2016-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changsu Lee ,  Sungsoo Moon ,  Kemsuk Seo ,  Bongjae Rhee ,  Sangmoon Lee

IPC: H04R1/10 ,  H04M1/725 ,  H04M1/02 ,  H04R29/00

CPC classification number: H04M1/72527 ,  H04M1/0274 ,  H04R1/1041 ,  H04R29/001 ,  H04R2440/07

Abstract: An interface device and method between an electronic device and an external device using an ear jack of a smart device are disclosed in order to implement an interface that is capable of automatically recognizing an ear jack insertion type appcessory. The interface device includes: an electronic device including an ear jack including a plurality of audio signal input and output terminals; an external device including an interface unit including a connector unit configured to be inserted into the ear jack, the connector unit including a plurality of terminals that correspond to the plurality of audio signal input and output terminals provided in the ear jack of the electronic device, respectively; and a recognizing unit on the connector unit of the interface unit configured to recognize whether the external device is connected to the ear jack of the electronic device through a plurality of detections.

公开(公告)号：US20160227018A1

公开(公告)日：2016-08-04

申请号：US15011227

申请日：2016-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changsu Lee ,  Sungsoo Moon ,  Kemsuk Seo ,  Bongjae Rhee ,  Sangmoon Lee

IPC: H04M1/725

CPC classification number: H04M1/72527 ,  H04M1/0274 ,  H04R1/1041 ,  H04R29/001 ,  H04R2440/07

Abstract: An interface device and method between an electronic device and an external device using an ear jack of a smart device are disclosed in order to implement an interface that is capable of automatically recognizing an ear jack insertion type appcessory. The interface device includes: an electronic device including an ear jack including a plurality of audio signal input and output terminals; an external device including an interface unit including a connector unit configured to be inserted into the ear jack, the connector unit including a plurality of terminals that correspond to the plurality of audio signal input and output terminals provided in the ear jack of the electronic device, respectively; and a recognizing unit on the connector unit of the interface unit configured to recognize whether the external device is connected to the ear jack of the electronic device through a plurality of detections.

Abstract translation: 公开了使用智能设备的耳塞的电子设备和外部设备之间的接口设备和方法，以实现能够自动识别耳塞插入型接口的接口。 所述接口装置包括：电子设备，其包括具有多个音频信号输入和输出端子的耳塞; 包括接口单元的外部设备，所述接口单元包括被配置为插入到所述耳塞中的连接器单元，所述连接器单元包括对应于设置在所述电子设备的所述耳塞中的所述多个音频信号输入和输出端子的多个端子， 分别; 以及接口单元的连接器单元上的识别单元，被配置为通过多个检测来识别外部设备是否连接到电子设备的耳塞。

公开(公告)号：US12142671B2

公开(公告)日：2024-11-12

申请号：US17514008

申请日：2021-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Chan Suh ,  Sangmoon Lee ,  Yihwan Kim ,  Woo Bin Song ,  Dongsuk Shin ,  Seung Ryul Lee

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material.

公开(公告)号：US20240322039A1

公开(公告)日：2024-09-26

申请号：US18421001

申请日：2024-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyojin Kim ,  Jinbum Kim ,  Sangmoon Lee ,  Yongjun Nam ,  Ingeon Hwang

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/42392

Abstract: The integrated circuit device includes a fin-type active region extending in a first direction, a channel region on the fin-type active region, a gate line on the channel region and extending in a second direction, and a source/drain region on the fin-type active region and in contact with the channel region, wherein the source/drain region includes a plurality of semiconductor layers including a first semiconductor layer that includes a portion in contact with the channel region and a portion in contact with the fin-type active region, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, a germanium (Ge) content ratio in the first semiconductor layer is greater than or equal to 10 at % and less than 100 at %, and the Ge content ratio in the first semiconductor layer decreases towards a boundary with the second semiconductor layer.

公开(公告)号：US20240321885A1

公开(公告)日：2024-09-26

申请号：US18476688

申请日：2023-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim ,  Ingyu Jang ,  Sujin Jung ,  Gyeom Kim ,  Hyojin Kim ,  Yongjun Nam ,  Sangmoon Lee

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823814 ,  H01L21/823871

Abstract: An integrated circuit device includes a first transistor comprising a first conductivity type, which includes a first channel region and a first source/drain region, a second transistor comprising a second conductivity type, which includes a second channel region and a second source/drain region, a first contact structure that contacts the first source/drain region and comprising a first length, and the first contact structure extends from above the first source/drain region and beyond an uppermost surface of the first channel region by a first vertical distance, and a second contact structure that contacts the second source/drain region and having a second length that is greater than the first length, the second contact extends from above the second source/drain region and beyond an uppermost surface of the second channel region by a second vertical distance, which is greater than the first vertical distance.

公开(公告)号：US12094975B2

公开(公告)日：2024-09-17

申请号：US18360457

申请日：2023-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangmoon Lee ,  Kyungin Choi ,  Seunghun Lee

IPC: H01L31/113 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L31/119

CPC classification number: H01L29/785 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/6681

Abstract: An active pattern structure includes a lower active pattern protruding from an upper surface of a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a buffer structure on the lower active pattern, at least a portion of which may include aluminum silicon oxide, and an upper active pattern on the buffer structure.

公开(公告)号：US20220336214A1

公开(公告)日：2022-10-20

申请号：US17853990

申请日：2022-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： GYEOM KIM ,  Dongwoo Kim ,  Jihye Yi ,  JINBUM KIM ,  Sangmoon Lee ,  Seunghun Lee

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L23/485 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L29/775

Abstract: A semiconductor device is provided. The semiconductor device includes: an active region on a semiconductor substrate; a channel region on the active region; a source/drain region adjacent to the channel region on the active region; a gate structure overlapping the channel region, on the channel region; a contact structure on the source/drain region; a gate spacer between the contact structure and the gate structure; and a contact spacer surrounding a side surface of the contact structure. The source/drain region includes a first epitaxial region having a recessed surface and a second epitaxial region on the recessed surface of the first epitaxial region, and the second epitaxial region includes an extended portion, extended from a portion overlapping the contact structure in a vertical direction, in a horizontal direction and overlapping the contact spacer in the vertical direction.

公开(公告)号：US20200219976A1

公开(公告)日：2020-07-09

申请号：US16666958

申请日：2019-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan KIM ,  Sunguk Jang ,  Pankwi Park ,  Sangmoon Lee ,  Sujin Jung

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device including an active fin that protrudes from a substrate and forms a plurality of recess regions spaced apart from each other, a gate pattern between the plurality of recess regions that covers a lateral surface and a top surface of the active fin, a plurality of source/drain patterns in the plurality of recess regions, and a diffusion reduction region adjacent to each of a plurality of bottoms of the plurality of recess regions and each of a plurality of sidewalls of the plurality of recess regions, the diffusion reduction region including a dopant having a lower diffusion coefficient than phosphorus (P).

公开(公告)号：US10692993B2

公开(公告)日：2020-06-23

申请号：US15956166

申请日：2018-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Chan Suh ,  Sangmoon Lee ,  Yihwan Kim ,  Woo Bin Song ,  Dongsuk Shin ,  Seung Ryul Lee

IPC: H01L21/82 ,  H01L29/66 ,  H01L21/28 ,  H01L29/786 ,  H01L29/423 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material.

公开(公告)号：US12278271B2

公开(公告)日：2025-04-15

申请号：US17514379

申请日：2021-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dahye Kim ,  Jinbum Kim ,  Jaemun Kim ,  Sangmoon Lee ,  Seung Hun Lee

IPC: H01L29/165 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a substrate including a peripheral region, a first active pattern on the peripheral region, the first active pattern having an upper portion including first semiconductor patterns and second semiconductor patterns, which are alternately stacked, a first gate electrode intersecting the first active pattern, a pair of first source/drain patterns provided at both sides of the first gate electrode, respectively, a first capping layer on the first active pattern, a second capping layer on the first capping layer, and a first gate insulating layer between the second capping layer and the first gate electrode. The first capping layer is between a sidewall of the first active pattern and the second capping layer. A concentration of germanium (Ge) of the first capping layer is greater than a concentration of germanium of the second capping layer.