公开(公告)号：US08969162B2

公开(公告)日：2015-03-03

申请号：US13933772

申请日：2013-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

IPC: H01L21/336 ,  H01L21/768 ,  H01L27/115

CPC classification number: H01L21/768 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

Abstract: Provided is a three-dimensional semiconductor device and method for fabricating the same. The device includes a first electrode structure and a second electrode structure stacked sequentially on a substrate. The first and second electrode structures include stacked first electrodes and stacked second electrodes, respectively. Each of the first and second electrodes includes a horizontal portion parallel with the substrate and an extension portion extending from the horizontal portion along a direction penetrating an upper surface of the substrate. Here, the substrate may be closer to top surfaces of the extension portions of the first electrodes than to the horizontal portion of at least one of the second electrodes.

Abstract translation: 提供一种三维半导体器件及其制造方法。 该装置包括依次堆叠在基板上的第一电极结构和第二电极结构。 第一和第二电极结构分别包括堆叠的第一电极和堆叠的第二电极。 第一和第二电极中的每一个包括平行于基板的水平部分和从穿过基板的上表面的方向从水平部分延伸的延伸部分。 这里，衬底可以比第一电极的延伸部分的顶表面更靠近至少一个第二电极的水平部分。

公开(公告)号：US12094846B2

公开(公告)日：2024-09-17

申请号：US18349017

申请日：2023-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Ho Ahn ,  Ji Won Kim ,  Sung-Min Hwang ,  Joon-Sung Lim ,  Suk Kang Sung

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/535 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L24/08 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/535 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A nonvolatile memory device including a substrate extending in a first direction, a ground selection line extending in the first direction on the substrate, a plurality of word lines stacked sequentially on the ground selection line and extending in the first direction, a landing pad spaced apart from the ground selection line and the plurality of word lines in the first direction, a rear contact plug connected to a lower face of the landing pad and extending in a second direction intersecting the first direction, a front contact plug connected to an upper face of the landing pad opposite the lower face and extending in the second direction, an input/output pad electrically connected to the rear contact plug, and an upper bonding pad electrically connected to the front contact plug and connected to at least a part of a plurality of circuit elements of the nonvolatile memory device.

公开(公告)号：US12009325B2

公开(公告)日：2024-06-11

申请号：US17328176

申请日：2021-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min Hwang ,  Jiwon Kim ,  Jaeho Ahn ,  Joon-Sung Lim ,  Sukkang Sung

IPC: H01L23/00 ,  G11C16/08 ,  G11C16/10 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L24/08 ,  G11C16/08 ,  G11C16/10 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40 ,  H01L2224/08135 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor device and electronic system, the device including a cell structure stacked on a peripheral circuit structure, wherein the cell structure includes a first interlayer dielectric layer and first metal pads exposed at the first interlayer dielectric layer and connected to gate electrode layers and channel regions, the peripheral circuit structure includes a second interlayer dielectric layer and second metal pads exposed at the second interlayer dielectric layer and connected to a transistor, the first metal pads include adjacent first and second sub-pads, the second metal pads include adjacent third and fourth sub-pads, the first and third sub-pads are coupled, and a width of the first sub-pad is greater than that of the third sub-pad, and the second sub-pad and the fourth sub-pad are coupled, and a width of the fourth sub-pad is greater than that of the second sub-pad.

公开(公告)号：US20240098990A1

公开(公告)日：2024-03-21

申请号：US18127404

申请日：2023-03-28

Applicant: Samsung Electronics Co., Ltd

Inventor： Sung-Min Hwang ,  Jaehoon Lee ,  Seunghyun Cho ,  Jae-Joo Shim ,  Dong-Sik Lee

IPC: H01L29/76 ,  H01L23/528

CPC classification number: H10B41/27 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/35

Abstract: A semiconductor device includes a gate stack structure including insulating patterns and conductive patterns which are alternately stacked, a first separation structure penetrating the gate stack structure, a second separation structure penetrating the gate stack structure and being adjacent to the first separation structure, first and second memory channel structures penetrating the gate stack structure and disposed between the first separation structure and the second separation structure, a first bit line overlapping with the first and second memory channel structures and electrically connected to the first memory channel structure, and a second bit line overlapping with the first and second memory channel structures and the first bit line and electrically connected to the second memory channel structure.

公开(公告)号：US11930639B2

公开(公告)日：2024-03-12

申请号：US17706426

申请日：2022-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woosung Yang ,  Dong-Sik Lee ,  Sung-Min Hwang ,  Joon-Sung Lim

IPC: H01L23/522 ,  H01L21/28 ,  H01L23/528 ,  H01L29/66 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/66545 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A three-dimensional semiconductor memory device may include horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other, memory structures provided on the horizontal patterns, respectively, each of the memory structures including a three-dimensional arrangement of memory cells. Penetrating insulating patterns and separation structures may isolate the horizontal patterns from one another. Through vias may extend through the penetrating insulating patterns to connect logic circuits of the peripheral circuit structure to the memory structure.

公开(公告)号：US11456236B2

公开(公告)日：2022-09-27

申请号：US16722418

申请日：2019-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo-Sung Yang ,  Joon-Sung Lim ,  Sung-Min Hwang ,  Ji-Young Kim ,  Ji-Won Kim

IPC: H01L23/48 ,  H01L27/11582 ,  H01L27/11575

Abstract: A vertical semiconductor device including a plurality of vertical memory cells on an upper surface of a first substrate, an adhesive layer on a lower surface of the first substrate that is opposite to the upper surface of the first substrate, a second substrate having first peripheral circuits thereon, a lower insulating interlayer on the second substrate, and a plurality of wiring structures electrically connecting the vertical memory cells and the first peripheral circuits. A lower surface of the adhesive layer and an upper surface of the lower insulating interlayer may be in contact with each other.

公开(公告)号：US10903236B2

公开(公告)日：2021-01-26

申请号：US16663228

申请日：2019-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kangyoon Choi ,  Dong-Sik Lee ,  Jongwon Kim ,  Gilsung Lee ,  Eunsuk Cho ,  Byungyong Choi ,  Sung-Min Hwang

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/04 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/28 ,  H01L21/02

Abstract: A three-dimensional (3D) semiconductor memory device includes a substrate that includes a cell array region and a connection region, a dummy trench formed on the connection region, an electrode structure on the substrate and that includes vertically stacked electrodes that have a staircase structure on the connection region, a dummy insulating structure disposed in the dummy trench, the dummy insulating structure including an etch stop pattern spaced apart from the substrate and the electrode structure, a cell channel structure disposed on the cell array region and that penetrates the electrode structure and makes contact with the substrate, and a dummy channel structure disposed on the connection region and that penetrates the electrode structure and a portion of the dummy insulating structure and that makes contact with the etch stop pattern.

公开(公告)号：US10886299B2

公开(公告)日：2021-01-05

申请号：US16901171

申请日：2020-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min Hwang ,  Joon-Sung Lim ,  Jihye Kim

IPC: H01L27/118 ,  H01L23/538 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573

Abstract: A semiconductor memory device includes a body conductive layer that includes a cell array portion and a peripheral circuit portion, an electrode structure on the cell array portion of the body conductive layer, vertical structures that penetrate the electrode structure, a residual substrate on the peripheral circuit portion of the body conductive layer, and a connection conductive pattern penetrating the residual substrate. The electrode structure includes a plurality of electrode that are stacked on top of each other. The vertical structures are connected to the cell array portion of the body conductive layer. The connection conductive pattern is connected to the peripheral circuit portion of the body conductive layer.

公开(公告)号：US10727244B2

公开(公告)日：2020-07-28

申请号：US15982001

申请日：2018-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min Hwang ,  Joon-Sung Lim ,  Eunsuk Cho

IPC: H01L27/115 ,  H01L27/11573 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11582 ,  H01L25/065 ,  H01L27/11575

Abstract: A semiconductor memory device includes a first semiconductor chip and a second semiconductor chip. Each semiconductor chip of the first and second semiconductor chips may include a cell array region and a peripheral circuit region. The cell array region may include an electrode structure including electrodes sequentially stacked on a body conductive layer and vertical structures extending through the electrode structure and connected to the body conductive layer. The peripheral circuit region may include a residual substrate on the body conductive layer and on which a peripheral transistor is located. A bottom surface of the body conductive layer of the second semiconductor chip may face a bottom surface of the body conductive layer of the first semiconductor chip.

公开(公告)号：US10461030B2

公开(公告)日：2019-10-29

申请号：US15331224

申请日：2016-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min Hwang ,  Young-Ho Lee ,  Seong-Soon Cho ,  Woon-Kyung Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11582

Abstract: Step shape pad structure and wiring structure in vertical type semiconductor device are include a first conductive line having a first line shape and including first pad regions at an upper surface of an edge portion, and a second conductive line having s second line shape and being spaced apart from the first conductive line and provided on the first conductive line. An end portion of the first conductive line is extended to a first position. Second pad regions are included on an upper surface of an edge portion of the second conductive line. An end portion of the second conductive line is extended to the first position. The second conductive line includes a dent portion at a facing portion to the first pad regions in a vertical direction to expose the first pad regions. The pad structure may be used in a vertical type nonvolatile memory device.