公开(公告)号：US20240250144A1

公开(公告)日：2024-07-25

申请号：US18585978

申请日：2024-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghoon Lee ,  Jongho Park ,  Wandon Kim ,  Sangjin Hyun

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/3215 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853 ,  H01L21/3115 ,  H01L21/3215

Abstract: A semiconductor device includes a substrate having first and second active regions, first and second active patterns on the first and second active regions, first and second gate electrodes running across the first and second active patterns, and a high-k dielectric layer between the first active pattern and the first gate electrode and between the second active pattern and the second gate electrode. The first gate electrode includes a work function metal pattern and an electrode pattern. The second gate electrode includes a first work function metal pattern, a second work function metal pattern, and an electrode pattern. The first work function metal pattern contains the same impurity as that of the high-k dielectric layer. An impurity concentration of the first work function metal pattern of the second gate electrode is greater than that of the work function metal pattern of the first gate electrode.

公开(公告)号：US20240250088A1

公开(公告)日：2024-07-25

申请号：US18600403

申请日：2024-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon Tae Hwang ,  Sunjung Lee ,  Heonbok Lee ,  Geunwoo Kim ,  Wandon Kim

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871

Abstract: A semiconductor device includes a first and second channel patterns on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; and a second interface layer interposed between the second source/drain pattern and the second contact plug, the first and second interface layers including different metallic elements from each other, a bottom portion of the second interface layer being positioned at a level that is lower than a bottom surface of a topmost one of the semiconductor patterns.

公开(公告)号：US11955523B2

公开(公告)日：2024-04-09

申请号：US18113116

申请日：2023-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Namgyu Cho ,  Minwoo Song ,  Ohseong Kwon ,  Wandon Kim ,  Hyeokjun Son ,  Jinkyu Jang

IPC: H01L29/417 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/41791 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/4236 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7854 ,  H01L29/7855 ,  H01L29/78696 ,  H01L29/4966 ,  H01L29/7848

Abstract: A semiconductor device includes: an active fin disposed on a substrate; a gate structure overlapping the active fin; source/drain regions disposed on both sides of the gate structure and on the active fin; and contact structures respectively connected to the source/drain regions, wherein the gate structure includes: a pair of gate spacers spaced apart from each other to provide a trench; a first gate electrode disposed in the trench and extending along an upper surface and a lateral surface of the active fin; a second gate electrode disposed on the first gate electrode in the trench, wherein the first gate electrode is not disposed between the second gate electrode and the pair of gate spacers; and a gate insulating film disposed between the pair of gate spacers and interposed between the first gate electrode and the active fin.

公开(公告)号：US11955487B2

公开(公告)日：2024-04-09

申请号：US17886878

申请日：2022-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon Tae Hwang ,  Sunjung Lee ,  Heonbok Lee ,  Geunwoo Kim ,  Wandon Kim

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871

Abstract: A semiconductor device includes a first and second channel patterns on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; and a second interface layer interposed between the second source/drain pattern and the second contact plug, the first and second interface layers including different metallic elements from each other, a bottom portion of the second interface layer being positioned at a level that is lower than a bottom surface of a topmost one of the semiconductor patterns.

公开(公告)号：US20230253310A1

公开(公告)日：2023-08-10

申请号：US18299926

申请日：2023-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok LEE ,  Donggon Yoo ,  Wandon Kim

IPC: H01L23/522 ,  H01L29/06 ,  H01L29/08 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L29/0649 ,  H01L29/0847 ,  H01L23/5283

Abstract: A semiconductor device including transistors on a substrate, a first interlayer insulating layer on the transistors, a first lower interconnection line and a second lower interconnection line in an upper portion of the first interlayer insulating layer, a dielectric layer being selectively on a top surface of the first interlayer insulating layer except top surfaces of the first and second lower interconnection lines, an etch stop layer on the first and second lower interconnection lines and the dielectric layer, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer may be provided.

公开(公告)号：US11335701B2

公开(公告)日：2022-05-17

申请号：US16780006

申请日：2020-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghoon Lee ,  Jongho Park ,  Musarrat Hasan ,  Wandon Kim ,  Seungkeun Cha

IPC: H01L27/1159 ,  H01L29/78 ,  H01L27/11585 ,  H01L29/51

Abstract: A semiconductor device includes a substrate, a channel on or in the substrate, a source/drain pair respectively on opposite ends of the channel, and a gate structure on the channel between the source/drain pair, wherein the gate structure includes an interfacial layer, a ferroelectric layer, a stabilization layer, an oxygen diffusion barrier layer, and a threshold voltage control layer that are sequentially stacked on the channel.

公开(公告)号：US20210028291A1

公开(公告)日：2021-01-28

申请号：US16886881

申请日：2020-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongho Park ,  Byounghoon Lee ,  Seungkeun Cha ,  Wandon Kim

IPC: H01L29/49 ,  H01L29/45 ,  H01L29/10 ,  H01L29/423 ,  H01L29/06

Abstract: Semiconductor devices are provided. A semiconductor device includes a first active pattern on a first region of a substrate, a pair of first source/drain patterns on the first active pattern, a first channel pattern between the pair of first source/drain patterns, and a gate electrode that extends across the first channel pattern. The gate electrode is on an uppermost surface and at least one sidewall of the first channel pattern. The gate electrode includes a first metal pattern including a p-type work function metal, a second metal pattern on the first metal pattern and including an n-type work function metal, a first barrier pattern on the second metal pattern and including an amorphous metal layer that includes tungsten (W), carbon (C), and nitrogen (N), and a second barrier pattern on the first barrier pattern. The second barrier pattern includes the p-type work function metal.

公开(公告)号：US20140103491A1

公开(公告)日：2014-04-17

申请号：US14022865

申请日：2013-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beomseok Kim ,  Ohseong Kwon ,  Wandon Kim ,  Jaewan Chang ,  Kyuho Cho

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/75 ,  H01L28/91

Abstract: The present inventive concept provides semiconductor devices that may include a capacitor including a lower electrode, a dielectric layer, and an upper electrode which are sequentially stacked. An electrode-protecting layer may be provided on the capacitor. The upper electrode may include a conductive metal oxide and the electrode-protecting layer may include a sacrificial reaction layer including a metal-hydrogen compound.

Abstract translation: 本发明构思提供半导体器件，其可以包括依次层叠的包括下电极，电介质层和上电极的电容器。 可以在电容器上设置电极保护层。 上电极可以包括导电金属氧化物，并且电极保护层可以包括包含金属 - 氢化合物的牺牲反应层。

公开(公告)号：US12218046B2

公开(公告)日：2025-02-04

申请号：US18299926

申请日：2023-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok Lee ,  Donggon Yoo ,  Wandon Kim

IPC: H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08

Abstract: A semiconductor device including transistors on a substrate, a first interlayer insulating layer on the transistors, a first lower interconnection line and a second lower interconnection line in an upper portion of the first interlayer insulating layer, a dielectric layer being selectively on a top surface of the first interlayer insulating layer except top surfaces of the first and second lower interconnection lines, an etch stop layer on the first and second lower interconnection lines and the dielectric layer, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer may be provided.

公开(公告)号：US12080712B2

公开(公告)日：2024-09-03

申请号：US17712272

申请日：2022-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghoon Lee ,  Jongho Park ,  Wandon Kim ,  Sangjin Hyun

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/4966 ,  H01L21/02532 ,  H01L21/28088 ,  H01L21/30604 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device includes a plurality of semiconductor patterns that are sequentially stacked and spaced apart from each other on a substrate, and a gate electrode on the plurality of semiconductor patterns. The gate electrode includes a capping pattern and a work function pattern that are sequentially stacked on the plurality of semiconductor patterns. The capping pattern includes a first metal nitride layer including a first metal element, and a second metal nitride layer including a second metal element whose work function is greater than a work function of the first metal element. The first metal nitride layer is disposed between the second metal nitride layer and the plurality of semiconductor patterns. The first metal nitride layer is thinner than the second metal nitride layer.