公开(公告)号：US09953981B2

公开(公告)日：2018-04-24

申请号：US15207554

申请日：2016-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-ik Kim ,  Hyoung-sub Kim ,  Yoo-sang Hwang ,  Ji-young Kim

IPC: H01L21/4763 ,  H01L27/108 ,  H01L21/311 ,  H01L21/762 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/10823 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76224 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891

Abstract: A method of manufacturing a semiconductor device includes: forming bit line structures spaced apart from each other by first groove disposed in first direction, extending in first direction, and spaced apart from each other in second direction perpendicular to first direction, on substrate in which word line is buried; forming multilayer spacer on both sidewalls of bit line structure; forming sacrificial layer to fill first groove; forming second grooves spaced apart from each other in first direction and second direction, by patterning sacrificial layer; etching outermost spacer of multilayer spacer located in second groove; forming first supplementary spacer in second groove; forming insulating layer to fill second groove; and forming third grooves spaced apart from each other in first direction and second direction, on both sides of first supplementary spacer, by removing sacrificial layer and insulating layer.

公开(公告)号：US09576902B2

公开(公告)日：2017-02-21

申请号：US15240156

申请日：2016-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je-min Park ,  Yoo-sang Hwang

IPC: H01L23/48 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/528 ,  H01L24/02 ,  H01L24/08 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/15313

Abstract: A semiconductor device includes conductive lines spaced from a substrate, and an insulating spacer structure between the conductive lines and defining a contact hole. The insulating spacer structure is adjacent a side wall of at least one of the conductive lines. The device also includes an insulating pattern on the conductive lines and insulating spacer structure, and another insulating pattern defining a landing pad hole connected to the contact hole. A contact plug is formed in the contact hole and connects to the active area. A landing pad is formed in the landing pad hole and connects to the contact plug. The landing pad vertically overlaps one of the pair of conductive line structures.

Abstract translation: 半导体器件包括与衬底间隔开的导线，以及在导线之间的绝缘间隔结构，并限定接触孔。 绝缘间隔物结构邻近至少一条导电线的侧壁。 该装置还包括导电线上的绝缘图案和绝缘间隔结构，以及限定连接到接触孔的着陆焊盘孔的另一绝缘图案。 接触插塞形成在接触孔中并且连接到有源区域。 着陆垫形成在着陆垫孔中并连接到接触塞。 着陆垫垂直地重叠一对导线结构之一。

公开(公告)号：US11251307B2

公开(公告)日：2022-02-15

申请号：US16120705

申请日：2018-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-jin Park ,  Jin-bum Kim ,  Bong-soo Kim ,  Kyu-pil Lee ,  Hyeong-sun Hong ,  Yoo-sang Hwang

IPC: H01L29/786 ,  H01L29/778 ,  H01L29/88 ,  H01L21/02 ,  H01L29/06 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/86 ,  H01L29/24

Abstract: A device includes a substrate, a first electrode on the substrate, an insulating pattern on the substrate, a second electrode on an upper end of the insulating pattern, a two-dimensional (2D) material layer on a side surface of the insulating pattern, a gate insulating layer covering the 2D material layer, and a gate electrode contacting the gate insulting layer. The insulating pattern extends from the first electrode in a direction substantially vertical to the substrate. The 2D material layer includes at least one atomic layer of a 2D material that is substantially parallel to the side surface of the insulating pattern.

公开(公告)号：US10600646B2

公开(公告)日：2020-03-24

申请号：US16120728

申请日：2018-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-jin Park ,  Bong-soo Kim ,  Jin-bum Kim ,  Yoo-sang Hwang

IPC: H01L21/02 ,  H01L29/786 ,  H01L29/66 ,  H01L29/778 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/20 ,  H01L29/16 ,  H01L29/24

Abstract: A method of fabricating a device including a two-dimensional (2D) material includes forming an amorphous transition metal oxide structure on a substrate and replacing the amorphous transition metal oxide structure by a transition metal dichalcogenide structure. The transition metal dichalcogenide structure includes atomic layers, that are substantially parallel to a surface of the transition metal dichalcogenide structure.

公开(公告)号：US10580876B2

公开(公告)日：2020-03-03

申请号：US15914611

申请日：2018-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-hyeok Ahn ,  Eun-jung Kim ,  Hui-jung Kim ,  Ki-seok Lee ,  Bong-soo Kim ,  Myeong-dong Lee ,  Sung-hee Han ,  Yoo-sang Hwang

IPC: H01L29/423 ,  H01L21/74 ,  H01L21/762 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

Abstract: An integrated circuit device may include a pair of line structures. Each line structure may include a pair of conductive lines extending over a substrate in a first horizontal direction and a pair of insulating capping patterns respectively covering the pair of conductive lines. The integrated circuit device may include a conductive plug between the pair of line structures and a metal silicide film contacting a top surface of the conductive plug between the pair of insulating capping patterns. The conductive plug may have a first width between the pair of conductive lines and a second width between the pair of insulating capping patterns, in a second horizontal direction perpendicular to the first horizontal direction, where the second width is greater than the first width.

公开(公告)号：US10515798B2

公开(公告)日：2019-12-24

申请号：US16120775

申请日：2018-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-jin Park ,  Bong-soo Kim ,  Jin-bum Kim ,  Yoo-sang Hwang

IPC: H01L21/02 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/778 ,  H01L29/24 ,  H01L29/16 ,  H01L29/20

Abstract: A method of fabricating a device including a two-dimensional (2D) material includes forming a transition metal oxide pattern on a substrate and forming a transition metal dichalcogenide layer on a top surface and a side surface of a residual portion of the transition metal oxide pattern. The forming the transition metal dichalcogenide layer may include replacing a surface portion of the transition metal oxide pattern with the transition metal dichalcogenide layer. The transition metal dichalcogenide layer includes at least one atomic layer that is substantially parallel to a surface of the residual portion of the transition metal oxide pattern.

公开(公告)号：US20190164976A1

公开(公告)日：2019-05-30

申请号：US16004937

申请日：2018-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hui-jung Kim ,  Bong-soo Kim ,  Sung-hee Han ,  Yoo-sang Hwang

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/768

Abstract: A semiconductor memory device according to an example embodiment of the present inventive concept may include: a plurality of lower electrodes located on a substrate and spaced apart from one another; and an etch stop pattern located on the substrate and surrounding at least a part of each of the plurality of lower electrodes, in which the etch stop pattern includes: a first etch stop pattern including carbon; and a second etch stop pattern located on the first etch stop pattern and including a material different from a material of the first etch stop pattern.

公开(公告)号：US11482285B2

公开(公告)日：2022-10-25

申请号：US16936917

申请日：2020-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-woo Kim ,  Jae-Kyu Lee ,  Ki-seok Suh ,  Hyeong-sun Hong ,  Yoo-sang Hwang ,  Gwan-hyeob Koh

IPC: H01L23/528 ,  H01L43/12 ,  G11C14/00 ,  H01L45/00 ,  H01L29/08 ,  H01L27/108 ,  H01L29/423 ,  H01L43/08 ,  H01L43/02 ,  H01L27/24 ,  H01L27/22 ,  H01L27/105 ,  H01L27/02 ,  G11C7/10 ,  G11C11/00

Abstract: An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.

公开(公告)号：US20190189617A1

公开(公告)日：2019-06-20

申请号：US16014118

申请日：2018-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-jung KIM ,  Sung-hee Han ,  Ki-seok Lee ,  Bong-soo Kim ,  Yoo-sang Hwang

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10817 ,  H01L27/10852 ,  H01L28/91

Abstract: An integrated circuit device may include a support pattern over a substrate, a lower electrode pattern and a dielectric structure over the substrate, and an upper electrode structure on the dielectric structure. The support pattern may include a first support structure extending in a vertical direction. The lower electrode pattern may be between the support pattern and the dielectric structure. The lower electrode pattern may include a first group of N (e.g., an integer of 4 or more) lower electrodes that are spaced apart from each other and may extend in the vertical direction to a first level above the substrate. The dielectric structure may include a first dielectric protrusion that extends in the vertical direction and surrounds the first support structure and the first group of N lower electrodes. The upper electrode structure may include a first upper electrode protrusion that surrounds the first dielectric protrusion.

公开(公告)号：US20190074381A1

公开(公告)日：2019-03-07

申请号：US16120726

申请日：2018-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-jin Park ,  Jin-bum Kim ,  Bong-soo Kim ,  Kyu-pil Lee ,  Hyeong-sun Hong ,  Yoo-sang Hwang

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H01L29/86 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06

Abstract: A device including a two-dimensional (2D) material includes a substrate including a recess recessed from a main surface of the substrate and extending in a first direction, a 2D material pattern on the substrate and intersecting with the recess of the substrate, a gate structure contacting the 2D material pattern and extending in the first direction along the recess of the substrate, a first electrode contacting a first end of the 2D material pattern, and a second electrode contacting a second end of the 2D material pattern. The 2D material pattern extends in a second direction and includes atomic layers that are parallel to a surface of the substrate.