公开(公告)号：US10651224B2

公开(公告)日：2020-05-12

申请号：US16058451

申请日：2018-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim ,  Chajea Jo ,  Hyoeun Kim ,  Jongbo Shim ,  Sang-uk Han

IPC: H01L31/00 ,  H01L27/146 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip. A second semiconductor chip is below the first semiconductor chip. A third semiconductor chip is below the second semiconductor chip. The second semiconductor chip includes a first surface in direct contact with the first semiconductor chip, and a second surface facing the third semiconductor chip. A first redistribution pattern is on the second surface of the second semiconductor chip and is electrically connected to the third semiconductor chip. The third semiconductor chip includes a third surface facing the second semiconductor chip. A conductive pad is on the third surface.

公开(公告)号：US20240332270A1

公开(公告)日：2024-10-03

申请号：US18475863

申请日：2023-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangjin Baek ,  Kyung Don Mun ,  Ji Hwang Kim ,  Kyoung Lim Suk

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/16 ,  H01L21/56 ,  H01L23/3128 ,  H01L24/06 ,  H01L24/08 ,  H01L24/16 ,  H01L24/80 ,  H01L24/81 ,  H01L28/40 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81801

Abstract: The present disclosure relates to semiconductor packages and methods for manufacturing semiconductor packages. An example semiconductor package includes a top die, first and second bottom dies attached on a lower surface of the top die and being apart from each other by a preset distance, and at least one decoupling capacitor connected to the lower surface of the top die between the first bottom die and the second bottom die. The top die, the first bottom die, and the second bottom die are chiplets.

公开(公告)号：US12062605B2

公开(公告)日：2024-08-13

申请号：US18308433

申请日：2023-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim ,  Hyunkyu Kim ,  Jongbo Shim ,  Eunhee Jung ,  Kyoungsei Choi

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/45 ,  H01L25/0657

Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.

公开(公告)号：US11876083B2

公开(公告)日：2024-01-16

申请号：US17407647

申请日：2021-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongho Kim ,  Ji Hwang Kim ,  Hwan Pil Park ,  Jongbo Shim

IPC: H01L23/02 ,  H01L25/10 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L25/105 ,  H01L21/4882 ,  H01L25/0655 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094

Abstract: Provided is a semiconductor package comprising a lower package that includes a lower substrate and a lower semiconductor chip, an interposer substrate on the lower package and having a plurality of holes that penetrate the interposer substrate, a thermal radiation structure that includes a supporter on a top surface of the interposer substrate and a plurality of protrusions in the holes of the interposer substrate, and a thermal conductive layer between the lower semiconductor chip and the protrusions of the thermal radiation structure.

公开(公告)号：US11658107B2

公开(公告)日：2023-05-23

申请号：US17807894

申请日：2022-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim ,  Hyunkyu Kim ,  Jongbo Shim ,  Eunhee Jung ,  Kyoungsei Choi

IPC: H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/45 ,  H01L25/0657

Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.

公开(公告)号：US11367679B2

公开(公告)日：2022-06-21

申请号：US17017638

申请日：2020-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim ,  Hyunkyu Kim ,  Jongbo Shim ,  Eunhee Jung ,  Kyoungsei Choi

IPC: H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.

公开(公告)号：US10923428B2

公开(公告)日：2021-02-16

申请号：US16432551

申请日：2019-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim ,  Kilsoo Kim ,  Jongbo Shim ,  Jangwoo Lee ,  Eunhee Jung

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/498

Abstract: A semiconductor package includes a substrate, a semiconductor chip mounted on the substrate, an interposer chip on the semiconductor chip and including a redistribution pattern, a first pad on the interposer chip, a second pad on the interposer chip and spaced apart from the first pad, and a bonding wire electrically connected to the second pad and the first substrate. The second pad is electrically connected through the redistribution pattern to the first pad. The footprint of the interposer chip is greater than the footprint of the first semiconductor chip.

公开(公告)号：US20190214423A1

公开(公告)日：2019-07-11

申请号：US16058451

申请日：2018-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim ,  Chajea Jo ,  Hyoeun Kim ,  Jongbo Shim ,  Sang-uk Han

IPC: H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14634 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/16 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14687 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0557 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/16104 ,  H01L2224/16145

Abstract: A semiconductor package includes a first semiconductor chip. A second semiconductor chip is below the first semiconductor chip. A third semiconductor chip is below the second semiconductor chip. The second semiconductor chip includes a first surface in direct contact with the first semiconductor chip, and a second surface facing the third semiconductor chip. A first redistribution pattern is on the second surface of the second semiconductor chip and is electrically connected to the third semiconductor chip. The third semiconductor chip includes a third surface facing the second semiconductor chip. A conductive pad is on the third surface.

公开(公告)号：US11728230B2

公开(公告)日：2023-08-15

申请号：US17350329

申请日：2021-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim ,  Dongho Kim ,  Jin-Woo Park ,  Jongbo Shim

IPC: H01L23/13 ,  H01L25/10 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L23/13 ,  H01L21/4853 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/1023 ,  H01L2225/1058

Abstract: A semiconductor package includes: a lower package: an upper substrate on the lower package: and connection members connecting the lower package to the upper substrate, wherein the lower package includes: a lower substrate; and a lower semiconductor chip, wherein the upper substrate includes: an upper substrate body: upper connection pads combined with the connection members: and auxiliary members extending from the upper substrate body toward the lower substrate, wherein the connection members are arranged in a first horizontal direction to form a first connection member column, wherein the auxiliary members are arranged in the first horizontal direction to form a first auxiliary member column, wherein the first connection member column and the first auxiliary member column are located between a side surface of the lower semiconductor chip and a side surface of the lower substrate, and the first auxiliary member column is spaced apart from the first connection member column.

公开(公告)号：US11569201B2

公开(公告)日：2023-01-31

申请号：US17509750

申请日：2021-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoeun Kim ,  Ji Hwang Kim ,  Jisun Yang ,  Seunghoon Yeon ,  Chajea Jo ,  Sang-Uk Han

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first semiconductor structure and a second semiconductor structure that are on the first semiconductor chip and spaced apart from each other across the second semiconductor chip, and a resin-containing member between the second semiconductor chip and the first semiconductor structure and between the second semiconductor chip and the second semiconductor structure. The semiconductor package may be fabricated at a wafer level.