公开(公告)号：US20180357123A1

公开(公告)日：2018-12-13

申请号：US15934565

申请日：2018-03-23

Applicant: SanDisk Technologies LLC

Inventor： Yibo Yin ,  Henry Zhang ,  Po-Shen Lai ,  Vijay Chinchole ,  Spyridon Georgakis ,  Yan Li ,  Hiroyuki Mizukoshi ,  Toru Miwa ,  Jayesh Pakhale ,  Tz-Yi Liu

IPC: G06F11/10

CPC classification number: G06F11/1016 ,  G06F11/1064

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for a multicore on-die memory controller. An integrated circuit device includes an array of non-volatile memory cells and a microcontroller unit. A microcontroller unit includes a plurality of processing units. Different processing units perform different categories of tasks in parallel for an array of non-volatile memory cells.

公开(公告)号：US10127150B2

公开(公告)日：2018-11-13

申请号：US13749523

申请日：2013-01-24

Applicant: SanDisk Technologies LLC

Inventor： Steven T. Sprouse ,  Yan Li

IPC: G06F12/00 ,  G06F12/02 ,  G11C11/56 ,  G11C15/04 ,  G11C16/04 ,  G11C16/34 ,  G11C16/02

Abstract: A NAND Flash based content addressable memory (CAM) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as PCI-E, SAS, SATA, eMMC, SCSI, and so on. A host writes a key-value pair to the drive, where the drive writes the keys along bit lines of a CAM NAND portion of the drive and stores the value in the drive. The drive then maintains a table linking the keys to location of the value. In a read process, the host provides a key to drive, which then broadcasts down the word lines of blocks storing the keys. Based on any matching bit lines, the tables can then be used to retrieve and supply the corresponding data to the host.

公开(公告)号：US10121522B1

公开(公告)日：2018-11-06

申请号：US15630089

申请日：2017-06-22

Applicant: SanDisk Technologies LLC

Inventor： Tai-Yuan Tseng ,  Anirudh Amarnath ,  Yan Li

IPC: G11C16/10 ,  G11C7/08 ,  G11C11/16 ,  G11C13/00

Abstract: A sense circuit is provided in which the threshold voltage of a memory cell is sensed relative to two different levels using a single control gate voltage on the memory cell. These two levels can be higher and lower verify voltages of a data state in a programming operation, or two read levels of a read operation. Two sense nodes which are connected in a cascade configuration such that a first sense node discharges into the bit line initially, and a second sense node may or may not discharge into the bit line, depending on the level to which the first node has discharged. First and second bits of data can be output from the sense circuit based on the levels of the first and second sense nodes to indicate the threshold voltage of the memory cell relative to the higher and lower verify voltages, respectively.

公开(公告)号：US10120816B2

公开(公告)日：2018-11-06

申请号：US15458561

申请日：2017-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Wanfang Tsai ,  Yan Li

IPC: G06F13/16 ,  G06F5/06 ,  G11C16/34 ,  G06F3/06 ,  G11C16/04 ,  G11C16/10 ,  G11C29/00 ,  G11C7/10

Abstract: Systems and methods for controlling data flow and data alignment using data expand and compress circuitry arranged between a variable data rate bi-directional first in, first out (FIFO) buffer and one or more memory arrays to compensate for bad column locations within the one or more memory arrays are described. The bi-directional FIFO may have a variable data rate with the array side and a fixed data rate with a serializer/deserializer (SERDES) circuit that drives input/output (I/O) circuitry. The data expand and compress circuitry may pack and unpack data and then align the data passing between the one or more memory arrays and the bi-directional FIFO using a temporary buffer, data shuffling logic, and selective pipeline stalls.

公开(公告)号：US20180046231A1

公开(公告)日：2018-02-15

申请号：US15237139

申请日：2016-08-15

Applicant: SanDisk Technologies LLC

Inventor： Deepak Raghu ,  Pao-Ling Koh ,  Philip Reusswig ,  Chris Nga Yee Yip ,  Jun Wan ,  Yan Li

IPC: G06F1/20 ,  G06F3/06

CPC classification number: G06F1/206 ,  G06F1/3225 ,  G06F1/3275 ,  G06F3/0616 ,  G06F3/0653 ,  G06F3/0688

Abstract: A storage device with a memory may modify throttling to reduce cross temperature effects. The decision to throttle may be based on a memory device temperature (i.e. temperature throttling) or may be based on the memory device's health, usage, or performance (e.g. hot count or bit error rate). Temperature throttling may be implemented that considers the memory device's health, usage, or performance (e.g. hot count or bit error rate). Likewise, throttling based on the memory device's health, usage, or performance may utilize the memory device's temperature to optimize throttling time. For example, a test mode matrix (TMM) may be modified to depend on temperature.

公开(公告)号：US20220398438A1

公开(公告)日：2022-12-15

申请号：US17343228

申请日：2021-06-09

Applicant: SanDisk Technologies LLC

Inventor： Yanli Zhang ,  Yan Li

IPC: G06N3/063 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C11/54 ,  G11C16/10 ,  G11C16/24 ,  G06F7/523

Abstract: A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NOR architecture in which vertical NOR strings are formed of multiple memory cells connected in parallel between a source line and a bit line. Weights of the neural network are encoded as threshold voltages of the memory cells and activations are encoded as word line voltages applied to the memory cells of the NOR strings. The memory cells are operated in the subthreshold region, where the word line voltages are below the threshold voltages. The NOR structure naturally sums the resultant subthreshold currents of the individual memory cells to generate the product of the activations and the weights of the neural network by concurrently applying input voltages to multiple memory cells of a NOR string.

公开(公告)号：US11507498B2

公开(公告)日：2022-11-22

申请号：US16810243

申请日：2020-03-05

Applicant: SanDisk Technologies LLC

Inventor： Yuheng Zhang ,  Yan Li

IPC: G06F12/02 ,  G06F12/0877 ,  G06F1/24 ,  G06F9/30 ,  G06F9/445 ,  G06F13/16

Abstract: An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core Timing Control (CTC) signals that are used to control voltages applied in the memory structure. In one aspect, information from which the CTC signals may be generated is pre-computed and stored. This pre-computation may be performed in a power on phase of the memory system. When a request to perform a memory operation is received, the stored information may be accessed and used to generate the CTC signals to control the memory operation. Thus, considerable time and/or power is saved. Note that this time savings occurs each time the memory operation is performed. Also, power is saved due to not having to repeatedly perform the computation.

公开(公告)号：US11487548B2

公开(公告)日：2022-11-01

申请号：US16695759

申请日：2019-11-26

Applicant: SanDisk Technologies LLC

Inventor： Vijay Chinchole ,  Nisha Padattil Kuliyampattil ,  Sonam Agarwal ,  Akash Agarwal ,  Pavithra Devaraj ,  Yan Li

IPC: G11C7/00 ,  G06F9/38 ,  G06F9/34 ,  G06F12/02 ,  G06F9/54 ,  G06F11/30 ,  G06F9/22 ,  G06F3/06

Abstract: A non-volatile memory apparatus and corresponding method of operation are provided. The apparatus includes non-volatile memory cells in an integrated circuit device along with a microcontroller in communication with the non-volatile memory cells. The microcontroller is configured to receive a memory operation command and in response, determine a condition value of one of a plurality of conditions associated with the memory operation command and whether the one of the plurality of conditions is dynamic. In parallel, the microcontroller determines and outputs an output value using the condition value. The microcontroller then determines whether the one the plurality of conditions has changed. If the one of the plurality of conditions is dynamic and has changed, the microcontroller determines an updated condition value and in parallel, compares the condition value and the updated condition value and determines and outputs an updated output value using the updated condition value and the comparison.

公开(公告)号：US20220129163A1

公开(公告)日：2022-04-28

申请号：US17359945

申请日：2021-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： A Harihara Sravan ,  Yan Li ,  Feng Lu

IPC: G06F3/06

Abstract: An encoder of a storage medium receives, at a plurality of latches respectively associated with a plurality of memory cells, soft data corresponding to data subject to a read operation specified by the a storage controller, compresses the soft data, and stores the compressed soft data in a buffer before transmitting the compressed soft data to the storage controller. Upon the buffer being full, the encoder writes uncompressed soft data back to at least a subset of the plurality of latches, and upon completion of the writing of the uncompressed soft data, the encoder resumes compressing and storing of soft data in the buffer, and transmits the compressed soft data to the storage controller.

公开(公告)号：US11301176B2

公开(公告)日：2022-04-12

申请号：US16909484

申请日：2020-06-23

Applicant: SanDisk Technologies LLC

Inventor： Chi-Lin Hsu ,  Tai-Yuan Tseng ,  Yan Li ,  Hiroyuki Mizukoshi

IPC: G06F3/06 ,  G06F9/30 ,  G06F9/38 ,  G11C11/00 ,  G11C5/06 ,  G11C11/4072 ,  G06F8/65 ,  G11C29/16 ,  G11C5/14 ,  G11C16/28 ,  G11C11/56 ,  G11C29/46 ,  G11C16/34 ,  G11C16/24 ,  G11C16/10 ,  G11C16/08

Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.