Power FETS with improved high voltage performance
    13.
    发明授权
    Power FETS with improved high voltage performance 失效
    功率FETS具有改进的高电压性能

    公开(公告)号:US5043777A

    公开(公告)日:1991-08-27

    申请号:US593371

    申请日:1990-09-28

    IPC分类号: H01L29/778 H01L29/80

    CPC分类号: H01L29/7787 H01L29/802

    摘要: An undoped surface layer over and lattice matched to the n-channel layer between the gate contact and the spaced apart source and drain n+ regions in power FETs made of group III-V compounds minimizes surface effects that preclude such devices from operating efficiently at high voltages, and improves reliability. The undoped surface layer may be grown on the n-channel layer before the layer forming the n+ regions, or where the n+ regions can be formed in the undoped surface layer. The invention is especially suitable for GaAs MESFETs and HEMTs.

    摘要翻译: 在III-V族化合物制成的功率FET中栅极接触和间隔开的源极和漏极n +区之间的n沟道层上的未掺杂的表面层使表面效应最小化,从而使得这些器件不能在高电压下有效地工作 ,并提高可靠性。 在形成n +区的层之前,或者可以在未掺杂的表面层中形成n +区的情况下,可以在n沟道层上生长未掺杂的表面层。 本发明特别适用于GaAs MESFET和HEMT。

    Metal semiconductor field effect transistors (MESFETS) having channels of varying thicknesses and related methods
    14.
    发明授权
    Metal semiconductor field effect transistors (MESFETS) having channels of varying thicknesses and related methods 有权
    金属半导体场效应晶体管(MESFETS)具有不同厚度的沟道和相关方法

    公开(公告)号:US07402844B2

    公开(公告)日:2008-07-22

    申请号:US11289158

    申请日:2005-11-29

    IPC分类号: H01L29/778

    摘要: A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The unit cell includes a MESFET having a source, a drain and a gate. The gate is between the source and the drain and on a channel layer of the MESFET. The channel layer has a first thickness on a source side of the channel layer and a second thickness, thicker than the first thickness, on a drain side of the channel layer. Related methods of fabricating MESFETs are also provided herein.

    摘要翻译: 提供了一种金属半导体场效应晶体管(MESFET)的晶胞。 该单元包括具有源极,漏极和栅极的MESFET。 栅极位于源极和漏极之间以及MESFET的沟道层上。 沟道层在沟道层的漏极侧具有在沟道层的源极侧的第一厚度和比第一厚度更厚的第二厚度。 本文还提供了制造MESFET的相关方法。

    Asymetric layout structures for transistors and methods of fabricating the same
    15.
    发明授权
    Asymetric layout structures for transistors and methods of fabricating the same 有权
    晶体管的不对称布局结构及其制造方法

    公开(公告)号:US07265399B2

    公开(公告)日:2007-09-04

    申请号:US10977227

    申请日:2004-10-29

    IPC分类号: H01L29/80 H01L21/338

    摘要: High power transistors are provided. The transistors include a source region, a drain region and a gate contact. The gate contact is positioned between the source region and the drain region. First and second ohmic contacts are provided on the source and drain regions, respectively. The first and second ohmic contacts respectively define a source contact and a drain contact. The source contact and the drain contact have respective first and second widths. The first and second widths are different. Related methods of fabricating transistors are also provided.

    摘要翻译: 提供大功率晶体管。 晶体管包括源极区,漏极区和栅极接触。 栅极接触位于源极区域和漏极区域之间。 第一和第二欧姆触点分别设置在源极和漏极区域上。 第一和第二欧姆触点分别限定了源极触点和漏极触点。 源触点和漏极触点具有相应的第一和第二宽度。 第一和第二宽度是不同的。 还提供了制造晶体管的相关方法。

    Delta doped silicon carbide metal-semiconductor field effect transistors having a gate disposed in a double recess structure
    16.
    发明授权
    Delta doped silicon carbide metal-semiconductor field effect transistors having a gate disposed in a double recess structure 有权
    具有设置在双凹槽结构中的栅极的Δ掺杂碳化硅金属半导体场效应晶体管

    公开(公告)号:US06906350B2

    公开(公告)日:2005-06-14

    申请号:US10136456

    申请日:2001-10-24

    摘要: The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a delta doped silicon carbide MESFET having a source, a drain and a gate. The gate is situated between the source and the drain and extends into a doped channel layer of a first conductivity type. Regions of silicon carbide adjacent to the source and the drain extend between the source and the gate and the drain and the gate, respectively. The regions of silicon carbide have carrier concentrations that are greater than a carrier concentration of the doped channel layer and are spaced apart from the gate.

    摘要翻译: 本发明提供了一种金属半导体场效应晶体管(MESFET)的单元。 MESFET的单元包括具有源极,漏极和栅极的δ掺杂碳化硅MESFET。 栅极位于源极和漏极之间并延伸到第一导电类型的掺杂沟道层中。 与源极和漏极相邻的碳化硅区域分别在源极和栅极以及漏极和栅极之间延伸。 碳化硅的区域具有大于掺杂沟道层的载流子浓度并且与栅极间隔开的载流子浓度。

    Silicon carbide static induction transistor
    17.
    发明授权
    Silicon carbide static induction transistor 失效
    碳化硅静电感应晶体管

    公开(公告)号:US5612547A

    公开(公告)日:1997-03-18

    申请号:US462405

    申请日:1995-06-05

    摘要: A static induction transistor fabricated of silicon carbide, preferably 6H polytype, although any silicon carbide polytype may be used. The preferred static induction transistor is the recessed Schottky barrier gate type. Thus, a silicon carbide substrate is provided. Then, a silicon carbide drift layer is provided upon the substrate, wherein the drift layer has two spaced-apart protrusions or fingers which extend away from the substrate. Each protrusion of the drift layer has a source region of silicon carbide provided thereon. A gate material is then provided along the drift layer between the two protrusions. A conductive gate contact is provided upon the gate material and a conductive source contact is provided upon each source region. A conductive drain contact is provided along the substrate. Other gate types for the static induction transistor are contemplated. For example, a planar Schottky barrier gate may be employed. Furthermore, recessed or planar MOS gates may be utilized, as may a PN junction gate.

    摘要翻译: 尽管可以使用任何碳化硅多型体,但由碳化硅制成的静电感应晶体管,优选为6H型。 优选的静态感应晶体管是凹入的肖特基势垒栅型。 因此,提供了碳化硅衬底。 然后,在基板上设置碳化硅漂移层,其中漂移层具有远离衬底延伸的两个间隔开的突起或指状物。 漂移层的每个突起具有设置在其上的碳化硅源区域。 然后沿两个突起之间的漂移层提供栅极材料。 在栅极材料上提供导电栅极触点,并且在每个源极区域上提供导电源极触点。 沿着衬底提供导电漏极接触。 考虑静态感应晶体管的其他栅极类型。 例如,可以采用平面肖特基势垒栅极。 此外,可以使用凹入或平面的MOS栅极,如PN结栅极。

    Solid state micro-machined mass spectrograph universal gas detection
sensor
    18.
    发明授权
    Solid state micro-machined mass spectrograph universal gas detection sensor 失效
    固态微加工质谱仪通用气体检测传感器

    公开(公告)号:US5386115A

    公开(公告)日:1995-01-31

    申请号:US124873

    申请日:1993-09-22

    IPC分类号: H01J49/28 D01D59/44 H01J49/00

    CPC分类号: H01J49/288 H01J49/0018

    摘要: A solid state mass spectrograph includes an inlet, a gas ionizer, a mass filter and a detector array all formed within a cavity in a semiconductor substrate. The gas ionizer can be a solid state electron emitter with ion optics provided by electrodes formed on apertured partitions in the cavity forming compartments through which the cavity is evacuated by differential pumping. The mass filter is preferably a Wien filter with the magnetic field provided by a permanent magnet outside the substrate or by magnetic film on the cavity walls. The electric field of the Wien filter is provided by electrodes formed on walls of the cavity. The detector array is a linear array oriented in the dispersion plane of the mass filter and includes converging electrodes at the end of the cavity serving as Faraday cages which pass charge to signal generators such as charge coupled devices formed in the substrate but removed from the cavity.

    摘要翻译: 固态质谱仪包括全部形成在半导体衬底的空腔内的入口,气体离子发生器,质量过滤器和检测器阵列。 气体离子发生器可以是具有离子光学器件的固态电子发射器,该离子光学器件由形成在空腔形成室中的多孔分隔壁上的电极提供,空腔通过差分泵送而被排空。 质量过滤器优选为具有由基板外部的永磁体提供的磁场或在腔壁上的磁性膜提供的维恩滤波器。 维恩滤波器的电场由形成在空腔的壁上的电极提供。 检测器阵列是在质量过滤器的色散平面中定向的线性阵列,并且包括在用作法拉第笼的腔的端部处的会聚电极,其将电荷传递到信号发生器,例如形成在衬底中的电荷耦合器件,但是从腔 。

    Schottky Diodes Including Polysilicon Having Low Barrier Heights and Methods of Fabricating the Same
    19.
    发明申请
    Schottky Diodes Including Polysilicon Having Low Barrier Heights and Methods of Fabricating the Same 有权
    包括具有低阻挡高度的多晶硅的肖特基二极管及其制造方法

    公开(公告)号:US20100308337A1

    公开(公告)日:2010-12-09

    申请号:US12477376

    申请日:2009-06-03

    摘要: Hybrid semiconductor devices including a PIN diode portion and a Schottky diode portion are provided. The PIN diode portion is provided on a semiconductor substrate and has an anode contact on a first surface of the semiconductor substrate. The Schottky diode portion is also provided on the semiconductor substrate and includes a polysilicon layer on the semiconductor substrate and a ohmic contact on the polysilicon layer. Related Schottky diodes are also provided herein.

    摘要翻译: 提供了包括PIN二极管部分和肖特基二极管部分的混合半导体器件。 PIN二极管部分设置在半导体衬底上,并且在半导体衬底的第一表面上具有阳极接触。 肖特基二极管部分也设置在半导体衬底上并且包括在半导体衬底上的多晶硅层和多晶硅层上的欧姆接触。 本文还提供了相关的肖特基二极管。

    Transistors having buried p-type layers coupled to the gate
    20.
    发明授权
    Transistors having buried p-type layers coupled to the gate 有权
    晶体管具有连接到栅极的p型层

    公开(公告)号:US07646043B2

    公开(公告)日:2010-01-12

    申请号:US11536143

    申请日:2006-09-28

    IPC分类号: H01L29/10

    摘要: A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The MESFET has a source, a drain and a gate. The gate is between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the gate between the source and the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel layer and electrically coupled to the gate. Related methods are also provided herein.

    摘要翻译: 提供了一种金属半导体场效应晶体管(MESFET)的晶胞。 MESFET具有源极,漏极和栅极。 栅极在源极和漏极之间以及n型导电沟道层之间。 在源极和漏极之间的栅极下方提供p型导电区域。 p型导电区域与n型导电沟道层间隔开并电耦合到栅极。 本文还提供了相关方法。