公开(公告)号：US09842920B1

公开(公告)日：2017-12-12

申请号：US15208456

申请日：2016-07-12

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul Jeon ,  Chun-Li Liu

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L23/50

CPC classification number: H01L29/778 ,  H01L23/50 ,  H01L29/0696 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/4238

Abstract: Implementations of semiconductor devices may include: an isolated drain finger, a gate ring, and a source ring; wherein the gate ring surrounds a perimeter of the isolated drain finger; wherein the source ring surrounds an outer perimeter of the gate ring and the isolated drain finger; wherein a gate bus is coupled to the gate ring; wherein a first electrically insulative portion is located between the isolated drain finger and the gate ring; and wherein a second electrically insulative portion is located between the gate and the source ring.

公开(公告)号：US09773895B2

公开(公告)日：2017-09-26

申请号：US15133644

申请日：2016-04-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Balaji Padmanabhan ,  Prasad Venkatraman ,  Peter Moens ,  Mihir Mudholkar ,  Joe Fulton ,  Philip Celaya ,  Stephen St. Germain ,  Chun-Li Liu ,  Jason McDonald ,  Alexander Young ,  Ali Salih

IPC: H01L29/15 ,  H01L29/747 ,  H01L29/74 ,  H01L23/495 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423 ,  H01L29/778 ,  H01L25/11 ,  H03K17/687 ,  H01L23/00 ,  H01L27/088 ,  H01L21/8258 ,  H01L27/06

CPC classification number: H01L29/747 ,  H01L21/8258 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/40 ,  H01L25/115 ,  H01L25/18 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0883 ,  H01L29/205 ,  H01L29/404 ,  H01L29/4238 ,  H01L29/7416 ,  H01L29/742 ,  H01L29/7786 ,  H01L29/7787 ,  H01L2224/0603 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/00014 ,  H03K17/6874 ,  H03K2017/6878 ,  H03K2217/0009 ,  H03K2217/0018 ,  H01L2224/37099

Abstract: A half-bridge circuit can include a high-side HEMT, a high-side switch transistor, a low-side HEMT, and a low-side switch transistor. The die substrates of the HEMTs can be coupled to the sources of their corresponding switch transistors. In another aspect, a packaged electronic device for a half-bridge circuit can have a design that can use shorter connectors that help to reduce parasitic inductance and resistance. In a further aspect, a packaged electronic device for a half-bridge circuit can include more than one connection along the bottom of the package allows less lead connections along the periphery of the packaged electronic device and can allow for a smaller package.

公开(公告)号：US09620598B2

公开(公告)日：2017-04-11

申请号：US14741567

申请日：2015-06-17

Applicant: Semiconductor Components Industries, LLC

Inventor： Chun-Li Liu ,  Ali Salih

IPC: H01L29/15 ,  H01L29/20 ,  H01L29/786 ,  H01L29/778 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/2003 ,  H01L29/1083 ,  H01L29/404 ,  H01L29/42376 ,  H01L29/7783 ,  H01L29/78681 ,  H01L29/78696

Abstract: An electronic device can transistor having a channel layer that includes a compound semiconductor material. In an embodiment, the channel layer overlies a semiconductor layer that includes a carrier barrier region and a carrier accumulation region. The charge barrier region can help to reduce the likelihood that de-trapped carriers from the channel layer will enter the charge barrier region, and the charge accumulation region can help to repel carriers in the channel layer away from the charge barrier layer. In another embodiment, a barrier layer overlies the channel layer. Embodiments described herein may help to produce lower dynamic on-resistance, lower leakage current, another beneficial effect, or any combination thereof.

公开(公告)号：US20170025407A1

公开(公告)日：2017-01-26

申请号：US15196461

申请日：2016-06-29

Applicant: Semiconductor Components Industries, LLC

Inventor： Chun-Li Liu ,  Ali Salih

IPC: H01L27/06 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L49/02 ,  H01L29/866 ,  H01L27/02 ,  H01L29/205

CPC classification number: H01L27/0629 ,  H01L21/8258 ,  H01L27/0255 ,  H01L27/0288 ,  H01L27/0883 ,  H01L28/20 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66106 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/866 ,  H03K17/102 ,  H03K2217/0018

Abstract: In accordance with an embodiment, semiconductor component includes a compound semiconductor material based semiconductor device coupled to a silicon based semiconductor device and a protection element, wherein the silicon based semiconductor device is a transistor. The protection element is coupled in parallel across the silicon based semiconductor device and may be a resistor, a diode, or a transistor. In accordance with another embodiment, the silicon based semiconductor device is a diode. The compound semiconductor material may be shorted to a source of potential such as, for example, ground, with a shorting element.

Abstract translation: 根据实施例，半导体部件包括耦合到硅基半导体器件和保护元件的基于化合物半导体材料的半导体器件，其中硅基半导体器件是晶体管。 保护元件在硅​​基半导体器件上并联耦合，并且可以是电阻器，二极管或晶体管。 根据另一个实施例，硅基半导体器件是二极管。 化合物半导体材料可以用短路元件短路到诸如地面的电位源。

公开(公告)号：US20170025327A1

公开(公告)日：2017-01-26

申请号：US15205693

申请日：2016-07-08

Applicant: Semiconductor Components Industries, LLC

Inventor： Balaji Padmanabhan ,  Ali Salih ,  Prasad Venkatraman ,  Chun-Li Liu

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/4951 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49544 ,  H01L23/49562 ,  H01L24/09 ,  H01L24/89 ,  H01L2224/0916 ,  H01L2224/09181 ,  H01L2224/80001

Abstract: In accordance with an embodiment, a semiconductor component includes a support having first and second device receiving structures. A semiconductor device configured from a III-N semiconductor material is coupled to the support, wherein the semiconductor device has opposing surfaces. A first bond pad extends from a first portion of the first surface, a second bond pad extends from a second portion of the first surface, and a third bond pad extends from a third portion of the first surface. The first bond pad is coupled to the first device receiving portion, the drain bond pad is coupled to the second device receiving portion, and the third bond pad is coupled to the third lead. In accordance with another embodiment, a method includes coupling a semiconductor chip comprising a III-N semiconductor substrate material to a support.

公开(公告)号：US09257513B1

公开(公告)日：2016-02-09

申请号：US14452162

申请日：2014-08-05

Applicant: Semiconductor Components Industries, LLC

Inventor： Chun-Li Liu

IPC: H01L21/00 ,  H01L29/40 ,  H01L21/02 ,  H01L21/74

CPC classification number: H01L21/743 ,  H01L21/02304 ,  H01L21/746 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/404 ,  H01L29/872

Abstract: In accordance with an embodiment, a method for manufacturing a semiconductor component includes providing a semiconductor material having a surface and forming a passivation layer on the semiconductor material Portions of the passivation layer are removed and portions of the semiconductor material exposed by removing the portions of the passivation layer are also removed. A layer of dielectric material is formed on the passivation layer and the exposed portions of the semiconductor material and first and second cavities are formed in the layer of dielectric material. The first cavity exposes a first portion of the semiconductor material and has at least one step shaped sidewall and the second cavity exposes a second portion of the semiconductor material. A first electrode is formed in the first cavity and a second electrode is formed in the second cavity.

Abstract translation: 根据实施例，制造半导体部件的方法包括提供具有表面并在半导体材料上形成钝化层的半导体材料，去除钝化层的部分，并且通过去除部分 钝化层也被去除。 在钝化层上形成介电材料层，半导体材料的暴露部分和第一和第二空腔形成在电介质材料层中。 第一腔暴露半导体材料的第一部分并且具有至少一个阶梯形侧壁，并且第二腔暴露半导体材料的第二部分。 第一电极形成在第一腔中，第二电极形成在第二腔中。

公开(公告)号：US10276713B2

公开(公告)日：2019-04-30

申请号：US15487517

申请日：2017-04-14

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chun-Li Liu ,  Balaji Padmanabhan ,  Ali Salih ,  Peter Moens

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/20 ,  H01L29/10 ,  H01L29/778 ,  H01L21/74 ,  H01L29/78 ,  H01L21/768 ,  H01L21/762 ,  H01L29/417 ,  H01L21/76 ,  H01L21/763 ,  H01L21/02

Abstract: In accordance with an embodiment, a semiconductor component includes a plurality of layers of compound semiconductor material over a body of semiconductor material and first and second filled trenches extending into the plurality of layers of compound semiconductor material. The first trench has first and second sidewalls and a floor and a first dielectric liner over the first and second sidewalls and the second trench has first and second sidewalls and a floor and second dielectric liner over the first and second sidewalls of the second trench.

公开(公告)号：US09960234B2

公开(公告)日：2018-05-01

申请号：US14508266

申请日：2014-10-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Kirk Huang ,  Chun-Li Liu ,  Ali Salih

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/20 ,  H01L27/06 ,  H01L27/088

CPC classification number: H01L29/0696 ,  H01L27/0629 ,  H01L27/0883 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/78

Abstract: In one embodiment, a method of forming an MOS transistor includes forming a threshold voltage (Vth) of the MOS transistor to have a first value at interior portions of the MOS transistor and a second value at other locations within the MOS transistor that are distal from the interior portion wherein the second value is less than the first value.

公开(公告)号：US09620443B2

公开(公告)日：2017-04-11

申请号：US15208703

申请日：2016-07-13

Applicant: Semiconductor Components Industries, LLC

Inventor： Balaji Padmanabhan ,  Prasad Venkatraman ,  Ali Salih ,  Chun-Li Liu ,  Phillip Celaya

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49575 ,  H01L21/4825 ,  H01L21/4882 ,  H01L23/3735 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49568 ,  H01L2224/0603 ,  H01L2224/16245 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2224/37099

Abstract: In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure, a second device receiving structure, a first lead and a second lead. A first semiconductor chip is coupled to the first device receiving structure and a second semiconductor chip is coupled to the first semiconductor chip and the second device receiving structure. The first semiconductor chip is configured from a silicon semiconductor material and has a gate bond pad, a source bond pad, and a drain bond pad, and the second semiconductor chip is configured from a gallium nitride semiconductor chip and has a gate bond pad, a source bond pad, and a drain bond pad. In accordance with another embodiment, a method for manufacturing a semiconductor component includes coupling a first semiconductor chip to a support and coupling a second semiconductor chip to the support.

公开(公告)号：US20170025339A1

公开(公告)日：2017-01-26

申请号：US15207626

申请日：2016-07-12

Applicant: Semiconductor Components Industries, LLC

Inventor： Chun-Li Liu ,  Ali Salih ,  Balaji Padmanabhan ,  Mingjiao Liu

IPC: H01L23/495 ,  H01L25/18 ,  H01L23/00 ,  H01L23/14

CPC classification number: H01L23/49575 ,  H01L23/3735 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/18 ,  H01L29/16 ,  H01L29/2003 ,  H01L2224/37099 ,  H01L2224/40105 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48145 ,  H01L2224/48245 ,  H01L2224/49112 ,  H01L2224/49176 ,  H01L2224/49177 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/1306 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/85399

Abstract: A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode.

Abstract translation: 半导体部件包括具有与其一体形成的引线的支撑件。 绝缘金属基板安装在支撑体的表面上，半导体芯片安装在绝缘金属基板上。 基于III-N的半导体芯片安装到绝缘金属基板上，其中III-N基半导体芯片具有栅极焊盘，漏极接合焊盘和源极焊盘。 硅基半导体芯片安装在基于III-N的半导体芯片上。 根据实施例，硅基半导体芯片包括具有栅极接合焊盘，漏极接合焊盘和源极焊盘的器件。 III-N型半导体芯片的漏极接合焊盘可以结合到衬底或引线上。 根据另一个实施例，硅基半导体芯片是二极管。