公开(公告)号：US06849564B2

公开(公告)日：2005-02-01

申请号：US10376796

申请日：2003-02-27

申请人： Sheng Teng Hsu ,  Wei Pan ,  Wei-Wei Zhuang ,  Fengyan Zhang

发明人： Sheng Teng Hsu ,  Wei Pan ,  Wei-Wei Zhuang ,  Fengyan Zhang

IPC分类号： G11C13/00 ,  H01L27/10 ,  H01L27/24 ,  H01L21/00

CPC分类号： H01L27/24 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/72 ,  H01L27/10

摘要： A low-capacitance one-resistor/one-diode (1R1D) R-RAM array with a floating p-well is provided. The fabrication method comprises: forming an integrated circuit (IC) substrate; forming an n-doped buried layer (buried n layer) of silicon overlying the substrate; forming n-doped silicon sidewalls overlying the buried n layer; forming a p-doped well of silicon (p-well) overlying the buried n layer; and, forming a 1R1D R-RAM array overlying the p-well. Typically, the combination of the buried n layer and the n-doped sidewalls form an n-doped well (n-well) of silicon. Then, the p-well is formed inside the n-well. In other aspects, the p-well has sidewalls, and the method further comprises: forming an oxide insulator overlying the p-well sidewalls, between the n-well and the R-RAM array.

摘要翻译： 提供具有浮动p-well的低电容单电阻/单二极管（1R1D）R-RAM阵列。 该制造方法包括：形成集成电路（IC）衬底; 形成覆盖在衬底上的硅的n掺杂掩埋层（n层）; 形成覆盖掩埋n层的n掺杂硅侧壁; 形成覆盖在掩埋n层上的硅（p阱）的p掺杂阱; 并且形成覆盖p阱的1R1D R-RAM阵列。 通常，掩埋n层和n掺杂侧壁的组合形成硅的n掺杂阱（n阱）。 然后，p阱形成在n阱内。 在其他方面，p阱具有侧壁，并且该方法还包括：在n阱和R-RAM阵列之间形成覆盖p阱侧壁的氧化物绝缘体。

公开(公告)号：US06939724B2

公开(公告)日：2005-09-06

申请号：US10640770

申请日：2003-08-13

申请人： Wei-Wei Zhuang ,  Tingkai Li ,  David R. Evans ,  Sheng Teng Hsu ,  Wei Pan

发明人： Wei-Wei Zhuang ,  Tingkai Li ,  David R. Evans ,  Sheng Teng Hsu ,  Wei Pan

IPC分类号： H01L27/04 ,  H01L21/20 ,  H01L21/822 ,  H01L45/00 ,  H01L21/00

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1608

摘要： A method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer includes depositing, by MOCVD, a seed layer of PCMO, in highly crystalline form, thin film, having a thickness of between about 50 Å to 300 Å, depositing a second PCMO thin film layer on the seed layer, by spin coating, having a thickness of between about 500 Å to 3000 Å, to form a combined PCMO layer; increasing the resistance of the combined PCMO film in a semiconductor device by applying a negative electric pulse of between about −4V to −5V, having a pulse width of between about 75 nsec to 1 μsec; and decreasing the resistance of the combined PCMO layer in a semiconductor device by applying a positive electric pulse of between about +2.5V to +4V, having a pulse width greater than 2.0 μsec.

公开(公告)号：US07214583B2

公开(公告)日：2007-05-08

申请号：US11130983

申请日：2005-05-16

申请人： Sheng Teng Hsu ,  Tingkai Li ,  David R. Evans ,  Wei-Wei Zhuang ,  Wei Pan

发明人： Sheng Teng Hsu ,  Tingkai Li ,  David R. Evans ,  Wei-Wei Zhuang ,  Wei Pan

IPC分类号： H01L21/8242

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1625

摘要： Asymmetrically structured memory cells and a fabrication method are provided. The method comprises: forming a bottom electrode; forming an electrical pulse various resistance (EPVR) first layer having a polycrystalline structure over the bottom electrode; forming an EPVR second layer adjacent the first layer, with a nano-crystalline or amorphous structure; and, forming a top electrode overlying the first and second EPVR layers. EPVR materials include CMR, high temperature super conductor (HTSC), or perovskite metal oxide materials. In one aspect, the EPVR first layer is deposited with a metalorganic spin coat (MOD) process at a temperature in the range between 550 and 700 degrees C. The EPVR second layer is formed at a temperature less than, or equal to the deposition temperature of the first layer. After a step of removing solvents, the MOD deposited EPVR second layer is formed at a temperature less than, or equal to the 550 degrees C.

摘要翻译： 提供了非对称结构的存储单元和制造方法。 该方法包括：形成底部电极; 在底部电极上形成具有多晶结构的电脉冲各种电阻（EPVR）第一层; 用纳米结晶或无定形结构形成邻近第一层的EPVR第二层; 并且形成覆盖在第一和第二EPVR层上的顶部电极。 EPVR材料包括CMR，高温超导体（HTSC）或钙钛矿金属氧化物材料。 在一个方面，EPVR第一层在550-700℃的温度范围内用金属有机旋涂（MOD）工艺沉积.EPVR第二层是在小于或等于沉积温度 的第一层。 在除去溶剂的步骤之后，将MOD沉积的EPVR第二层在小于或等于550℃的温度下形成。

公开(公告)号：US07157287B2

公开(公告)日：2007-01-02

申请号：US10855088

申请日：2004-05-27

申请人： Wei-Wei Zhuang ,  Tingkai Li ,  Wei Pan ,  David R. Evans ,  Sheng Teng Hsu

发明人： Wei-Wei Zhuang ,  Tingkai Li ,  Wei Pan ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L21/20

CPC分类号： C23C18/1216 ,  C23C18/1225 ,  C23C18/1241 ,  C23C18/1283 ,  C30B23/02 ,  C30B29/24 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147 ,  H01L45/1608

摘要： A method of fabricating a CMR thin film for use in a semiconductor device includes preparing a CMR precursor in the form of a metal acetate based acetic acid solution; preparing a wafer; placing a wafer in a spin-coating chamber; spin-coating and heating the wafer according to the following: injecting the CMR precursor into a spin-coating chamber and onto the surface of the wafer in the spin-coating chamber; accelerating the wafer to a spin speed of between about 1500 RPM to 3000 RPM for about 30 seconds; baking the wafer at a temperature of about 180° C. for about one minute; ramping the temperature to about 230° C.; baking the wafer for about one minute at the ramped temperature; annealing the wafer at about 500° C. for about five minutes; repeating said spin-coating and heating steps at least three times; post-annealing the wafer at between about 500° C. to 600° C. for between about one to six hours in dry, clean air; and completing the semiconductor device.

摘要翻译： 制造用于半导体器件的CMR薄膜的方法包括制备基于金属乙酸酯的乙酸溶液形式的CMR前体; 准备晶圆; 将晶片放置在旋涂室中; 根据以下步骤旋涂和加热晶片：将CMR前体注入旋涂室并在旋涂室中的晶片表面上; 将晶片加速至约1500RPM至3000RPM之间的旋转速度约30秒; 在约180℃的温度下烘烤晶片约1分钟; 将温度升高至约230℃; 在升温下烘烤晶片约1分钟; 在约500℃退火晶片约5分钟; 重复所述旋涂和加热步骤至少三次; 在约500℃至600℃之间将晶片退火约1至6小时，在干燥，干净的空气中进行退火; 并完成半导体器件。

公开(公告)号：US20060099724A1

公开(公告)日：2006-05-11

申请号：US11314222

申请日：2005-12-21

申请人： Sheng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei Pan ,  Wei-Wei Zhuang ,  David Evans ,  Masayuki Tajiri

发明人： Sheng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei Pan ,  Wei-Wei Zhuang ,  David Evans ,  Masayuki Tajiri

IPC分类号： H01L21/00 ,  H01L21/20

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/51 ,  G11C2213/56 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147

摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7-X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1-XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.

摘要翻译： 提供了一种用于形成缓冲层存储单元的方法。 该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。 在该方法的一些方面，半导体缓冲层由YBa 2 N 3 O 7-X（YBCO），氧化铟（In 2或2 O 3）或氧化钌（RuO 2 N 2），其厚度在10-200纳米（nm）的范围内。 顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr 1-X C x MnO 3（PCMO）存储膜，其中x在0.1之间的区域 和0.6，厚度在10至200nm的范围内。

公开(公告)号：US20050054119A1

公开(公告)日：2005-03-10

申请号：US10755654

申请日：2004-01-12

申请人： Sheng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei Pan ,  Wei-Wei Zhuang ,  David Evans ,  Masayuki Tajiri

发明人： Sheng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei Pan ,  Wei-Wei Zhuang ,  David Evans ,  Masayuki Tajiri

IPC分类号： H01L27/10 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00 ,  H01L21/00 ,  G11C11/00 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/51 ,  G11C2213/56 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147

摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7−X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1−XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.

摘要翻译： 提供了一种用于形成缓冲层存储单元的方法。 该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。 在该方法的某些方面，半导体缓冲层由厚度在10至200纳米（nm）范围内的YBa2Cu3O7-X（YBCO），氧化铟（In2O3）或氧化钌（RuO2）形成。 顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr1-XCaXMnO3（PCMO）记忆膜，其中x在0.1和0.6之间的区域中，厚度在10至200nm的范围内。

公开(公告)号：US07029982B1

公开(公告)日：2006-04-18

申请号：US10971387

申请日：2004-10-21

申请人： Wei-Wei Zhuang ,  David R. Evans ,  Fengyan Zhang ,  Sheng Teng Hsu

发明人： Wei-Wei Zhuang ,  David R. Evans ,  Fengyan Zhang ,  Sheng Teng Hsu

IPC分类号： H01L21/20

CPC分类号： H01L45/1608 ,  C23C18/1216 ,  C23C18/1225 ,  C23C18/1283 ,  C23C18/1295 ,  H01L21/31691 ,  H01L28/20 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A method of fabricating a doped-PCMO thin film layer includes preparing a PCMO precursor solution having a transition metal additive therein; and spin-coating the doped-PCMO spin-coating solution onto a wafer.

摘要翻译： 制造掺杂PCMO薄膜层的方法包括制备其中具有过渡金属添加剂的PCMO前体溶液; 并将掺杂的PCMO旋涂溶液旋涂到晶片上。

公开(公告)号：US06190963B1

公开(公告)日：2001-02-20

申请号：US09316661

申请日：1999-05-21

申请人： Fengyan Zhang ,  Sheng Teng Hsu ,  Jer-shen Maa ,  Wei-Wei Zhuang

发明人： Fengyan Zhang ,  Sheng Teng Hsu ,  Jer-shen Maa ,  Wei-Wei Zhuang

IPC分类号： H01L218242

CPC分类号： H01L28/75 ,  H01L21/28568 ,  H01L28/55

摘要： An Ir—M—O composite film has been provided that is useful in forming an electrode of a ferroelectric capacitor, where M includes a variety of refractory metals. The Ir combination film is resistant to high temperature annealing in oxygen environments. When used with an underlying barrier layer made from the same variety of M transition metals, the resulting conductive barrier also suppresses to diffusion of Ir into any underlying Si substrates. As a result, Ir silicide products are not formed, which degrade the electrode interface characteristics. That is, the Ir combination film remains conductive, not peeling or forming hillocks, during high temperature annealing processes, even in oxygen. The Ir—M—O conductive electrode/barrier structures are useful in nonvolatile FeRAM devices, DRAMs, capacitors, pyroelectric infrared sensors, optical displays, optical switches, piezoelectric transducers, and surface acoustic wave devices. A method for forming an Ir—M—O composite film barrier layer and an Ir—M—O composite film ferroelectric electrode are also provided.

摘要翻译： 已经提供了可用于形成铁电电容器的电极的Ir-M-O复合膜，其中M包括各种难熔金属。 Ir组合膜在氧气环境中耐高温退火。 当与由相同种类的M过渡金属制成的底层阻挡层一起使用时，所得到的导电屏障还抑制Ir扩散到任何下面的Si衬底中。 结果，不形成铱硅化物产物，这降低了电极界面的特性。 也就是说，即使在氧气中，Ir组合膜在高温退火过程中仍保持导电性，不会剥离或形成小丘。 Ir-M-O导电电极/屏障结构可用于非易失性FeRAM器件，DRAM，电容器，热释电红外传感器，光学显示器，光开关，压电换能器和表面声波器件。 还提供了形成Ir-M-O复合膜阻挡层和Ir-M-O复合膜铁电电极的方法。

公开(公告)号：US06897074B1

公开(公告)日：2005-05-24

申请号：US10794736

申请日：2004-03-03

申请人： Fengyan Zhang ,  Wei-Wei Zhuang ,  Jong-Jan Lee ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Wei-Wei Zhuang ,  Jong-Jan Lee ,  Sheng Teng Hsu

IPC分类号： H01L21/00 ,  H01L21/02 ,  H01L21/316 ,  H01L41/22

CPC分类号： H01L21/31691 ,  H01L28/55 ,  H01L41/317

摘要： A method for forming a doped PGO ferroelectric thin film, and related doped PGO thin film structures are described. The method comprising: forming either an electrically conductive or electrically insulating substrate; forming a doped PGO film overlying the substrate; annealing; crystallizing; and, forming a single-phase c-axis doped PGO thin film overlying the substrate, having a Curie temperature of greater than 200 degrees C. Forming a doped PGO film overlying the substrate includes depositing a doped precursor in the range between 0.1N and 0.5N, with a molecular formula of Pby-xMxGe3O11, where: M is a doping element; y=4.5 to 6; and, x=0.1 to 1. The element M can be Sn, Ba, Sr, Cd, Ca, Pr, Ho, La, Sb, Zr, or Sm.

摘要翻译： 描述了用于形成掺杂的PGO铁电薄膜的方法以及相关的掺杂PGO薄膜结构。 该方法包括：形成导电或电绝缘的衬底; 在衬底上形成掺杂的PGO膜; 退火; 结晶 并且形成覆盖在衬底上的单相c轴掺杂的PGO薄膜，其居里温度大于200℃。形成覆盖在衬底上的掺杂PGO膜包括沉积在0.1N和0.5之间的掺杂前体 N，具有分子式为Pb x Si x N x N x O 11，其中：M是掺杂物 元件; y = 4.5〜6; x = 0.1〜1。元素M可以是Sn，Ba，Sr，Cd，Ca，Pr，Ho，La，Sb，Zr或Sm。

公开(公告)号：US06537361B2

公开(公告)日：2003-03-25

申请号：US09822637

申请日：2001-03-30

申请人： Wei-Wei Zhuang ,  Fengyan Zhang ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Wei-Wei Zhuang ,  Fengyan Zhang ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L2122

CPC分类号： H01L21/02197 ,  C01G21/00 ,  C01P2002/86 ,  H01L21/02112 ,  H01L21/02175 ,  H01L21/02282 ,  H01L21/31604 ,  H01L21/31691

摘要： A method of synthesizing a PGO spin-coating precursor solution includes utilizing the starting materials of lead acetate trihydrate (Pb(OAc)2•3H2O) and germanium alkoxide (Ge(OR)4(R=C2H5 and CH(CH3)2)). The organic solvent is di(ethylene glycol) ethyl ether. The mixed solution of lead and di(ethylene glycol) ethyl ether is heated in an atmosphere of air at a temperature no greater than 185° C., and preferably no greater than 190° C. for a time period in a range of thirty minutes to four hours. During the heating step the color of the solution is monitored to determine when the reaction is complete and when decomposition of the desired product begins to take place. The solution is then added to germanium di(ethylene glycol) ethyl ether to make the PGO spin-coating solution. This second step also entails heating the solution to a temperature no greater than 190° C. for a time period in a range of 0.5 to 2.0 hours. The process results in a PGO precursor solution suitable for use in spin-coating.