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32 条记录 (耗时 0.021 秒)

    Field effect transistor and method for fabricating the same
    12.
    发明授权
    Field effect transistor and method for fabricating the same 有权
    场效应晶体管及其制造方法

    公开(公告)号：US08188520B2

    公开(公告)日：2012-05-29

    申请号：US13104537

    申请日：2011-05-10

    申请人： Tadashi Watanabe ,  Hajime Matsuda

    发明人： Tadashi Watanabe ,  Hajime Matsuda

    IPC分类号： H01L29/66

    CPC分类号： H01L29/7787 ,  H01L21/28581 ,  H01L21/28587 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/8128

    摘要： A method for fabricating a field effect transistor includes: forming an insulating film provided on a semiconductor layer, the insulating film having an opening via which a surface of the semiconductor layer is exposed and including silicon oxide; forming a Schottky electrode on the insulating film and in the opening, the Schottky electrode having an overhang portion and having a first contact layer that is provided in a region contacting the insulating film and contains oxygen, and a second contact layer that is provided on the first contact layer and contains a smaller content of oxygen than that of the first contact layer; and removing the insulating film by a solution including hydrofluoric acid.

    摘要翻译： 一种用于制造场效应晶体管的方法，包括：形成设置在半导体层上的绝缘膜，所述绝缘膜具有暴露所述半导体层的表面并且包括氧化硅的开口; 在所述绝缘膜上和所述开口中形成肖特基电极，所述肖特基电极具有突出部分，并且具有设置在与所述绝缘膜接触并包含氧的区域中的第一接触层，以及设置在所述绝缘膜上的第二接触层 第一接触层并且含有比第一接触层的氧更小的氧含量; 并通过包含氢氟酸的溶液除去绝缘膜。

    Switch circuit, semiconductor device, and method of manufacturing said semiconductor device
    13.
    发明申请
    Switch circuit, semiconductor device, and method of manufacturing said semiconductor device 有权
    开关电路，半导体器件和制造所述半导体器件的方法

    公开(公告)号：US20060219534A1

    公开(公告)日：2006-10-05

    申请号：US11391487

    申请日：2006-03-29

    申请人： Hajime Matsuda

    发明人： Hajime Matsuda

    IPC分类号： H01H9/28

    CPC分类号： H01L27/088 ,  H01L29/7785 ,  H01L29/7787 ,  H03K17/693

    摘要： A switch circuit includes: a first FET that is connected to one of an input terminal and an output terminal, and performs ON/OFF operation under the control of a gate electrode connected to a control terminal; and a second FET that is connected between the first FET and the other one of the input terminal and the output terminal, and performs ON/OFF operation under the control of a gate electrode connected to the control terminal. The first FET has a higher gate backward breakdown voltage than that of the second FET. Alternatively, the first FET has lower OFF capacitance than that of the second FET.

    摘要翻译： 开关电路包括：第一FET，其连接到输入端子和输出端子之一，并且在连接到控制端子的栅电极的控制下执行ON / OFF操作; 以及第二FET，其连接在第一FET与输入端子和输出端子中的另一个之间，并且在与控制端子连接的栅电极的控制下进行ON / OFF操作。 第一FET具有比第二FET高的栅极反向击穿电压。 或者，第一FET具有比第二FET低的OFF电容。

    Semiconductor device and method for fabricating the same
    14.
    发明授权
    Semiconductor device and method for fabricating the same 失效
    半导体装置及其制造方法

    公开(公告)号：US06316297B1

    公开(公告)日：2001-11-13

    申请号：US09436470

    申请日：1999-11-08

    申请人： Hajime Matsuda

    发明人： Hajime Matsuda

    IPC分类号： H01L21338

    CPC分类号： H01L29/66878 ,  H01L21/28587

    摘要： The method for fabricating a semiconductor device comprises the steps of forming on a semiconductor substrate a gate electrode, and an eave-shaped film of an inorganic material formed on the upper surface of the gate electrode and having a eave-shaped portion projected beyond the edge of the gate electrode; and ion-implanting a dopant with the gate electrode as a mask and with the eave-shaped portion of the eave-shaped film as a through film to form a first diffusion layer in the semiconductor substrate immediately below the eave-shaped portion and a second diffusion layer which is connected to the first diffusion layer, and is deeper and has a higher dopant concentration than the first diffusion layer, in the semiconductor substrate in a region where the eave-shaped film is not formed.

    摘要翻译： 制造半导体器件的方法包括以下步骤：在半导体衬底上形成栅电极和形成在栅电极的上表面上的无机材料的檐形膜，并且具有突出超过边缘的檐状部分 的栅电极; 以栅电极作为掩模离子注入掺杂剂，并以檐状膜的檐状部分为通膜，在正下方的半导体衬底中形成第一扩散层，第二 扩散层，其连接到第一扩散层，并且在未形成檐形膜的区域中的半导体衬底中比第一扩散层更深并且具有较高的掺杂剂浓度。

    Compound semiconductor device and method of manufacturing the same
    15.
    发明授权
    Compound semiconductor device and method of manufacturing the same 失效
    化合物半导体器件及其制造方法

    公开(公告)号：US06200838B1

    公开(公告)日：2001-03-13

    申请号：US09357770

    申请日：1999-07-21

    申请人： Kazutaka Inoue ,  Hajime Matsuda

    发明人： Kazutaka Inoue ,  Hajime Matsuda

    IPC分类号： H01L21338

    CPC分类号： H01L29/66878 ,  H01L27/0883 ,  H01L29/1029 ,  H01L29/812

    摘要： In a compound semiconductor device constituting a field effect transistor having a buried p region 3, a channel region 4 is formed thin and highly doped by n-type impurity, and the buried p region 3 is formed shallowly and highly doped by p-type impurity to compensate the highly doped channel region 4. In order to prevent a leakage current between the highly doped buried p region 3 and a gate electrode 5, a low concentration p-type impurity region 2 is formed on both sides of the highly doped buried p region 3 to thus prevent a current flow via a portion other than a channel region. Accordingly, there can be provided the compound semiconductor device including an FET which is able to suppress both the deterioration in the pinch-off characteristic and the leakage current between neighboring elements due to p-type impurity conduction other than a channel in an FET which has a high concentration and thin active layer, while suppressing the short channel effect.

    摘要翻译： 在构成具有埋入p区域3的场效应晶体管的化合物半导体器件中，沟道区域4形成为由n型杂质稀薄且高度掺杂，并且埋入p区3由p型杂质形成为浅掺杂 以补偿高掺杂沟道区4.为了防止高掺杂掩埋p区3和栅电极5之间的漏电流，在高掺杂掩埋p的两侧形成低浓度p型杂质区2 区域3，从而防止通过除了通道区域以外的部分的电流流动。 因此，可以提供一种化合物半导体器件，其包括FET，其能够抑制除了具有FET的沟道以外的p型杂质导电的夹断特性和相邻元件之间的漏电流的劣化 高浓度和薄的活性层，同时抑制短通道效应。

    High-speed semiconductor device having a dual-layer gate structure and a fabrication process thereof
    16.
    发明授权
    High-speed semiconductor device having a dual-layer gate structure and a fabrication process thereof 有权
    具有双层栅极结构的高速半导体器件及其制造方法

    公开(公告)号：US6037245A

    公开(公告)日：2000-03-14

    申请号：US340193

    申请日：1999-06-28

    申请人： Hajime Matsuda

    发明人： Hajime Matsuda

    IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/285 ,  H01L21/335 ,  H01L21/338 ,  H01L21/768 ,  H01L29/40 ,  H01L21/3205

    CPC分类号： H01L29/66878 ,  H01L21/28587 ,  H01L29/66462 ,  H01L21/7682 ,  H01L28/10

    摘要： A fabricating process of a semiconductor device includes the steps of forming a first photoresist layer on a surface of a substrate so as to cover a gate electrode on the substrate, forming a second photoresist layer on the fist photoresist layer with an increased sensitivity, forming a third photoresist layer on the second photoresist layer with a reduced sensitivity, forming an opening in a photoresist structure thus formed of the first through third photoresist layers such that the opening exposes the gate electrode and such that the opening has a diameter that increases gradually from the first photoresist layer to the second photoresist layer. Further, a low-resistance metal layer is deposited on the photoresist structure including the opening, such that the metal layer forms a low-resistance electrode on the gate electrode.

    摘要翻译： 半导体器件的制造方法包括以下步骤：在衬底的表面上形成第一光致抗蚀剂层，以覆盖衬底上的栅电极，在第一光致抗蚀剂层上以增加的灵敏度形成第二光致抗蚀剂层，形成 在第二光致抗蚀剂层上具有降低的灵敏度的第三光致抗蚀剂层，在由第一至第三光致抗蚀剂层形成的光致抗蚀剂结构中形成开口，使得开口暴露栅电极，使得开口具有从 第一光致抗蚀剂层到第二光致抗蚀剂层。 此外，在包括开口的光致抗蚀剂结构上沉积低电阻金属层，使得金属层在栅电极上形成低电阻电极。

    Charge transfer device having improved electrodes
    18.
    发明授权
    Charge transfer device having improved electrodes 失效
    电荷转移装置具有改进的电极

    公开(公告)号：US4589005A

    公开(公告)日：1986-05-13

    申请号：US500595

    申请日：1983-06-02

    申请人： Hajime Matsuda ,  Hiroshi Morito

    发明人： Hajime Matsuda ,  Hiroshi Morito

    IPC分类号： G11C27/04 ,  H01L21/339 ,  H01L29/423 ,  H01L29/76 ,  H01L29/762 ,  H01L29/768 ,  H01L29/772 ,  H01L29/78 ,  G11C19/28

    CPC分类号： H01L29/768 ,  H01L29/42396 ,  H01L29/76

    摘要： A charge transfer device in which a number of transfer electrodes, comprised of alternating main electrodes and auxiliary electrodes, are formed on but insulated from a channel region in a semiconductor substrate for transferring charges. The transfer electrodes are formed such that the sides of each of the electrodes which are transverse to the channel direction are concave in the direction of charge transfer. These concave sides produce an additional accelerating electric field which supplements the conventional fringing fields.

    摘要翻译： 一种电荷转移装置，其中由交替的主电极和辅助电极组成的多个转移电极形成在半导体衬底中，用于转移电荷但与沟道区绝缘。 转印电极被形成为使得每个电极的横向于沟道方向的侧面在电荷转移方向上是凹的。 这些凹面产生额外的加速电场，补充了传统的边缘场。

    Printing Quality Evaluation System, Laser Marking Apparatus, Printing Condition Setting Device, Printing Quality Evaluation Apparatus, Printing Condition Setting Program, Printing Quality Evaluation Program, And Computer-Readable Recording Medium
    19.
    发明申请
    Printing Quality Evaluation System, Laser Marking Apparatus, Printing Condition Setting Device, Printing Quality Evaluation Apparatus, Printing Condition Setting Program, Printing Quality Evaluation Program, And Computer-Readable Recording Medium 有权
    印刷质量评估系统，激光打标设备，印刷条件设置装置，印刷质量评估装置，印刷条件设定程序，印刷质量评估程序和计算机可读记录介质

    公开(公告)号：US20120182374A1

    公开(公告)日：2012-07-19

    申请号：US13348698

    申请日：2012-01-12

    申请人： Hajime Matsuda ,  Takaaki Ito

    发明人： Hajime Matsuda ,  Takaaki Ito

    IPC分类号： B41J2/47 ,  G06K15/02

    CPC分类号： G06K1/121 ,  G06F3/1208 ,  G06F3/1256 ,  G06K5/00 ,  G06K15/027 ,  G06K15/12

    摘要： In order to improve read stability, a printing condition is set based on not visual read of a user, but read with an optical information reading apparatus. A printing quality evaluation apparatus includes: an image acquiring section that acquires an image; a symbol extracting section that extracts the symbol in which the printing quality can be evaluated from the captured images acquired by the image acquiring section; a printing quality evaluation section that evaluates the printing quality of the symbol extracted by the symbol extracting section; an identification information recognition section that recognizes the identification information identifying each printing condition of the symbol; and an evaluation output section that outputs the identification information, which is recognized by the identification information recognition section, and an evaluation result of the printing quality of the printing quality evaluation section according to the symbol extracted by the symbol extracting section.

    摘要翻译： 为了提高读取稳定性，基于不是用户的可视读取来设置打印条件，而是用光学信息读取装置读取。 打印质量评估装置包括：图像获取部，其获取图像; 符号提取部，从由图像获取部获取的拍摄图像中提取可以评价打印质量的符号; 打印质量评估部，其评价由所述符号提取部提取的符号的打印质量; 识别信息识别部，其识别识别符号的每个打印条件的识别信息; 以及评价输出部，其输出由识别信息识别部识别的识别信息，以及根据由符号提取部提取的符号的打印质量评价部的打印质量的评价结果​​。

    Semiconductor device and manufacturing method of the same
    20.
    发明授权
    Semiconductor device and manufacturing method of the same 失效
    半导体器件及其制造方法相同

    公开(公告)号：US07087957B2

    公开(公告)日：2006-08-08

    申请号：US11034920

    申请日：2005-01-14

    申请人： Hajime Matsuda

    发明人： Hajime Matsuda

    IPC分类号： H01L29/76 ,  H01L29/94

    CPC分类号： H01L29/7783 ,  H01L27/0605 ,  H01L27/0883

    摘要： A semiconductor device includes a compound semiconductor substrate, a channel layer provided on the compound semiconductor substrate, a buried layer provided on the channel layer, a first recess formed in the buried layer in an E-mode region, a second recess formed in the first recess in the E-mode region and another second recess formed in the buried layer in a D-mode region, and a gate electrode provided in the second recess in the E-mode region and another gate electrode provided in the second recess in the D-mode region, and a distance between a surface of the buried layer and a bottom of the second recess in the E-mode region is shorter than another distance between another surface of the buried layer and a bottom of said another second recess in the D-mode region.

    摘要翻译： 半导体器件包括化合物半导体衬底，设置在化合物半导体衬底上的沟道层，设置在沟道层上的掩埋层，形成在E模式区域中的掩埋层中的第一凹部，形成在第一 在E模式区域中形成凹陷，在D模式区域中形成在掩埋层中的另一个第二凹槽，以及设置在E模式区域中的第二凹部中的栅极和设置在D模式区域中的第二凹部中的另一个栅电极 并且所述掩埋层的表面与所述E模式区域中的所述第二凹部的底部之间的距离短于所述掩埋层的另一表面与所述另一个第二凹部的D的底部之间的距离 模式区域。