公开(公告)号：US06455943B1

公开(公告)日：2002-09-24

申请号：US09840720

申请日：2001-04-24

Applicant: Shing-Ren Sheu ,  Hermen Liu

Inventor： Shing-Ren Sheu ,  Hermen Liu

IPC: H01L23485

CPC classification number: H01L24/05 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2224/45099

Abstract: A bonding pad structure of semiconductor device having improved bondability is disclosed. The bonding pad structure uses at least one level comprising conductive islands and conductive plugs used as fasteners to prevent the bonding pad layer from peeling and cracking during the bonding process.

Abstract translation: 公开了具有改善的粘合性的半导体器件的焊盘结构。 接合焊盘结构使用至少一个级别，包括用作紧固件的导电岛和导电插塞，以防止接合焊盘层在接合过程中剥离和破裂。

公开(公告)号：US06350654B1

公开(公告)日：2002-02-26

申请号：US09215618

申请日：1998-12-17

Applicant: Shing-Ren Sheu ,  Chung-Hsien Wu ,  Chih-Ming Huang

Inventor： Shing-Ren Sheu ,  Chung-Hsien Wu ,  Chih-Ming Huang

IPC: H01L21336

CPC classification number: H01L27/1126 ,  H01L27/105 ,  H01L27/11293

Abstract: A semiconductor read-only memory (ROM) and a method of fabricating the same are provided. The ROM device is structured in such a manner that allows the fabrication to include a fewer number of mask processes. This makes it more cost effective and allows a cycle time that is shorter than that of the prior art. Moreover, the particular structure of the ROM device makes punchthrough less likely to occur between any neighboring pairs of the buried bit lines when the ROM device is further scaled down. The ROM device is constructed on a semiconductor substrate which is partitioned into a peripheral region and a cell region. A plurality of STI structures are formed at predefined locations in both the peripheral region and the cell region. Immediately after this, a first ion-implantation process can be performed on the cell region to form a plurality of buried bit lines. Subsequently, the dielectric isolation layers in all of the STI structures in the cell region are removed, leaving a plurality of empty trenches behind. A conformal insulating layer and a conductive layer are then successively formed over the wafer, and the conductive layer is further selectively removed to form a word line in the cell region and a gate in the peripheral region. In the code implantation process, selected channel regions between the buried bit lines are doped with impurities for code implantation of data into the ROM device.

Abstract translation: 提供半导体只读存储器（ROM）及其制造方法。 ROM器件以允许制造包括更少数量的掩模处理的方式构造。 这使得它更具成本效益并且允许比现有技术更短的循环时间。 此外，当ROM器件进一步缩小时，ROM器件的特定结构使得在任何相邻的掩埋位线对之间不太可能发生穿透。 ROM器件被构造在被划分成周边区域和单元区域的半导体衬底上。 在周边区域和单元区域中的预定位置处形成多个STI结构。 此后，可以在单元区域上进行第一离子注入工艺以形成多个掩埋位线。 随后，去除单元区域中所有STI结构中的介电隔离层，留下多个空槽。 然后在晶片上连续地形成保形绝缘层和导电层，并且进一步选择性地去除导电层，以在单元区域中形成字线，并在外围区域形成栅极。 在代码注入过程中，掩埋位线之间的选定沟道区域掺杂有用于将数据代码注入到ROM器件中的杂质。

公开(公告)号：US5597753A

公开(公告)日：1997-01-28

申请号：US364318

申请日：1994-12-27

Applicant: Shing-Ren Sheu ,  Kuan-Cheng Su ,  Chen-Hui Chung ,  Yi-Chung Sheng

Inventor： Shing-Ren Sheu ,  Kuan-Cheng Su ,  Chen-Hui Chung ,  Yi-Chung Sheng

IPC: H01L21/8246

CPC classification number: H01L27/11246 ,  Y10S438/981

Abstract: An improved Read-Only-Memory (ROM) structure and a method of manufacturing said ROM device structure having an ultra-high-density of coded ROM cells, was achieved. The array of programmed ROM cells are composed of a single field effect transistor (FET) in each ROM cell. The improved ROM process utilizes the patterning of a ROM code insulating layer over each coded FET (cell) that is selected to remain in an off-state (nonconducting) when a gate voltage is applied. The remaining FETs (cells) have a thin gate oxide which switch to the on-state (conducting) when a gate voltage is applied. The thick ROM code insulating layer eliminates the need to code the FETs in the ROM memory cells by conventional high dose ion implantation. This eliminated the counter-doping of the buried bit lines by the implantation allowing for much tighter ground rules for the spacing between buried bit line. The elimination of the implant also reduces substantially the stand-by leakage current that is so important in battery operated electronic equipment, such as lap-top computers. The gate capacitance of the off-state cells is also substantially reduced because of the thick insulating layer, thereby reducing the RC time delay in the word lines and improving circuit performance.

Abstract translation: 实现了改进的只读存储器（ROM）结构和制造具有超高密度编码ROM单元的所述ROM器件结构的方法。 编程ROM单元的阵列由每个ROM单元中的单个场效应晶体管（FET）构成。 改进的ROM处理利用在施加栅极电压时选择为保持在截止状态（非导通）的每个编码的FET（单元）上的ROM代码绝缘层的图案化。 当施加栅极电压时，剩余的FET（单元）具有薄的栅极氧化物，其切换到导通状态（导通）。 粗ROM代码绝缘层消除了通过常规高剂量离子注入对ROM存储单元中的FET进行编码的需要。 这通过注入消除了掩埋位线的反掺杂，允许掩埋位线之间的间隔更紧密的基本规则。 植入物的消除也大大降低了备用泄漏电流，这在电池供电的电子设备如笔记本电脑中如此重要。 由于厚的绝缘层，断态单元的栅极电容也显着减小，从而减小了字线中的RC时间延迟并提高了电路性能。

公开(公告)号：US5488009A

公开(公告)日：1996-01-30

申请号：US344004

申请日：1994-11-23

Applicant: Chen-Chiu Hsue ,  Yi-Chung Shen ,  Shing-Ren Sheu ,  Chen-Hui Chung

Inventor： Chen-Chiu Hsue ,  Yi-Chung Shen ,  Shing-Ren Sheu ,  Chen-Hui Chung

IPC: H01L21/8246 ,  H01L27/112

CPC classification number: H01L27/1126 ,  H01L27/112 ,  Y10S257/915

Abstract: A method of manufacturing a code pattern on a semiconductor substrate with an array of substantially parallel buried bit lines integral therewith and with word lines above the buried bit lines, includes: forming a titanium nitride layer above the word lines, forming and patterning a code mask above the titanium nitride layer, implanting impurities into the substrate through openings in the code mask to form the code pattern, and performing rapid thermal annealing of the implant. The step height of the titanium nitride layer is employed to form the code identification on the substrate.

Abstract translation: 一种在半导体衬底上制造具有与其一体的基本上平行的掩埋位线阵列和掩埋位线之上的字线的阵列的方法，包括：在字线之上形成氮化钛层，形成码图掩模 在氮化钛层之上，通过编码掩模中的开口将杂质注入到衬底中，以形成编码图案，并对植入物进行快速热退火。 氮化钛层的台阶高度用于在基板上形成代码识别。

公开(公告)号：US5382534A

公开(公告)日：1995-01-17

申请号：US254534

申请日：1994-06-06

Applicant: Shing-Ren Sheu ,  Kuan-Cheng Su ,  Chen-Hui Chung

Inventor： Shing-Ren Sheu ,  Kuan-Cheng Su ,  Chen-Hui Chung

IPC: H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L21/265

CPC classification number: H01L29/66636 ,  H01L29/0847 ,  H01L29/1083

Abstract: The invention describes recessed buried conductive regions formed in a trench in the substrate that provides a smooth surface topology, smaller devices and improved device performance. The buried regions have two conductive regions, the first on the trench sidewalls, the second on the trench bottom. In addition, two buried layers are formed between adjacent buried conductive regions: a threshold voltage layer near the substrate surface and an anti-punchthrough layer formed at approximately the same depth as the conductive regions on the trench bottoms. The first conductive region and the anti-punchthrough layer have the effect of increasing the punchthru voltage without increasing the threshold voltage. The first and second regions also lowers the resistivity of the buried regions allowing use of smaller line pitches and therefore smaller devices. Overall, the recessed conductive regions and the two buried layers allow the formation of smaller devices with improved performance.

Abstract translation: 本发明描述了形成在衬底中的沟槽中的凹入的埋入导电区域，其提供了平滑的表面拓扑，较小的器件和改进的器件性能。 掩埋区域具有两个导电区域，第一个在沟槽侧壁上，第二个在沟槽底部。 此外，在相邻的掩埋导电区域之间形成两个掩埋层：在衬底表面附近的阈值电压层和形成在与沟槽底部上的导电区域大致相同深度的抗穿通层。 第一导电区域和抗穿通层具有增加穿透电压而不增加阈值电压的效果。 第一和第二区域也降低了掩埋区域的电阻率，从而允许使用较小的线间距并因此使用较小的器件。 总的来说，凹入的导电区域和两个掩埋层允许形成具有改进的性能的较小的器件。

公开(公告)号：US06417548B1

公开(公告)日：2002-07-09

申请号：US09356679

申请日：1999-07-19

Applicant: Shing-Ren Sheu ,  Cheng-Chih Kung

Inventor： Shing-Ren Sheu ,  Cheng-Chih Kung

IPC: H01L2976

CPC classification number: H01L27/11233 ,  H01L27/1052 ,  H01L27/112

Abstract: A mask ROM stores information by selecting the work function of the gates of each FET in an array of FETs. The polysilicon gates of some of the FETs are doped N-type and the gates of the other FETs are doped P-type to form gates having different work functions, thereby forming FETs having different threshold voltages. The ROM consists of a parallel array of buried N+ bit lines formed in the substrate, a gate oxide layer deposited over the bit lines and a layer of polysilicon deposited on the gate oxide. The polysilicon is blanket doped P-type and then an encoding mask is formed, with openings in the encoding mask exposing regions of the polysilicon to be formed into gates of FETs with low threshold voltages. Either arsenic or phosphorus is doped into the polysilicon through the mask openings. The mask is removed, a layer of conductive material such as tungsten silicide is deposited and the polysilicon and the conductive material are formed into word lines for the ROM. The word lines of the ROM serve as gates for the FETs and the bit lines serve as sources and drains for the FETs.

Abstract translation: 掩模ROM通过选择FET阵列中每个FET的栅极的功函数来存储信息。 一些FET的多晶硅栅极被掺杂为N型，并且其它FET的栅极被掺杂P型以形成具有不同功函数的栅极，从而形成具有不同阈值电压的FET。 该ROM由在衬底中形成的掩埋N +位线的平行阵列，沉积在位线上的栅极氧化物层和沉积在栅极氧化物上的多晶硅层组成。 多晶硅是覆盖掺杂P型，然后形成编码掩模，其中编码掩模中的开口暴露多晶硅的区域，以形成具有低阈值电压的FET的栅极。 砷或磷通过掩模开口掺杂到多晶硅中。 去除掩模，沉积诸如硅化钨的导电材料层，并且将多晶硅和导电材料形成为ROM的字线。 ROM的字线用作FET的栅极，位线用作FET的源极和漏极。

公开(公告)号：US6054353A

公开(公告)日：2000-04-25

申请号：US746855

申请日：1996-11-18

Applicant: Shing-Ren Sheu ,  Cheng-Chih Kung

Inventor： Shing-Ren Sheu ,  Cheng-Chih Kung

IPC: H01L21/8246 ,  H01L21/8234

CPC classification number: H01L27/11293 ,  H01L27/1126

Abstract: A mask ROM stores information by selecting the work function of the gates of each FET in an array of FETs at a late stage in the manufacture of the ROM. The polysilicon gates of some of the FETs are doped N-type and the gates of the other FETs are doped P-type to form gates having different work functions, thereby forming FETs having different threshold voltages. The ROM consists of a parallel array of buried N.sup.+ bit lines formed in the substrate, a gate oxide layer deposited over the bit lines and a layer of polysilicon deposited on the gate oxide. The polysilicon is blanket doped N-type, gate electrodes are defined by photolithography, and then self-aligned silicide layers are formed on the gate electrodes. An insulating layer is then formed over the gate electrodes. Programming of the ROM is accomplished by forming a mask on the insulating layer and then implanting ions through openings in the mask, through the insulating layer and the silicide layer, and into the polysilicon layer. The implantation converts individual gate electrodes from N-type to P-type to alter the threshold voltage of the selected transistors. Relatively few additional processing steps are needed after the programming to complete the ROM.

Abstract translation: 掩模ROM通过在ROM的制造中的晚期阶段选择FET的阵列中的每个FET的栅极的功函数来存储信息。 一些FET的多晶硅栅极被掺杂为N型，并且其它FET的栅极被掺杂P型以形成具有不同功函数的栅极，从而形成具有不同阈值电压的FET。 该ROM由在衬底中形成的掩埋N +位线的平行阵列，沉积在位线上的栅极氧化物层和沉积在栅极氧化物上的多晶硅层组成。 多晶硅是覆盖N掺杂的，栅极通过光刻法定义，然后在栅电极上形成自对准的硅化物层。 然后在栅电极上形成绝缘层。 ROM的编程通过在绝缘层上形成掩模然后通过掩模中的开口通过绝缘层和硅化物层注入离子并进入多晶硅层来实现。 注入将单个栅电极从N型转换为P型，以改变所选晶体管的阈值电压。 在编程完成ROM之后，需要较少的附加处理步骤。

公开(公告)号：US5589411A

公开(公告)日：1996-12-31

申请号：US508515

申请日：1995-07-28

Applicant: Sheng-Hsing Yang ,  Shing-Ren Sheu

Inventor： Sheng-Hsing Yang ,  Shing-Ren Sheu

IPC: H01L21/28 ,  H01L29/808 ,  H01L21/265

CPC classification number: H01L29/8083 ,  H01L21/2815

Abstract: A process for fabricating high-voltage MOSFET devices on a semiconductor substrate is disclosed. The substrate has heavily-doped impurities of a first conductivity type, and constitutes the drain region for the MOSFET. The process of fabrication comprises the steps of subsequently forming on the substrate a first doped layer, a second doped layer, a third doped layer and a shielding layer. All of these doped layers are of the first conductivity type. The second doped layer has an impurity concentration and a thickness smaller and larger than the impurity concentration and thickness respectively of the first doped layer, and larger and smaller than the impurity concentration and thickness respectively of the third doped layer. The impurity concentration of the first doped layer is smaller than the impurity concentration of the substrate. An opening in the shielding layer is formed, and then the source region of the MOSFET is formed in the area exposed by the opening. Afterwards, thermal oxidation is performed to form a field oxide layer over the surface of the source region. Next, an etching process is performed to remove the third doped layer, thereby revealing the surface of said second doped layer to form a source protruding body. Sidewalls of the source protruding body is then covered by an insulating layer. Finally, the field oxide layer and the insulating layer are then utilized as masking for implanting impurities of a second conductivity type into the second doped layer, thereby forming the gate region for the MOSFET.

Abstract translation: 公开了一种在半导体衬底上制造高压MOSFET器件的工艺。 衬底具有第一导电类型的重掺杂杂质，并且构成MOSFET的漏极区。 制造工艺包括随后在衬底上形成第一掺杂层，第二掺杂层，第三掺杂层和屏蔽层的步骤。 所有这些掺杂层都是第一导电类型。 第二掺杂层的杂质浓度和厚度分别小于和大于第一掺杂层的杂质浓度和厚度，并且分别大于和小于第三掺杂层的杂质浓度和厚度。 第一掺杂层的杂质浓度小于衬底的杂质浓度。 形成屏蔽层中的开口，然后在由开口暴露的区域中形成MOSFET的源极区域。 之后，进行热氧化以在源区域的表面上形成场氧化物层。 接下来，进行蚀刻处理以去除第三掺杂层，从而露出所述第二掺杂层的表面以形成源突出体。 源极突出体的侧壁然后被绝缘层覆盖。 最后，将场氧化物层和绝缘层用作掩模，以将第二导电类型的杂质注入到第二掺杂层中，从而形成用于MOSFET的栅极区域。

公开(公告)号：US5571737A

公开(公告)日：1996-11-05

申请号：US280113

申请日：1994-07-25

Applicant: Shing-Ren Sheu ,  Chung-Yuan Lee

Inventor： Shing-Ren Sheu ,  Chung-Yuan Lee

IPC: H01L21/336 ,  H01L27/02 ,  H01L21/265

CPC classification number: H01L29/66568 ,  H01L27/0251 ,  H01L27/0266

Abstract: An improved structure and process of fabricating a metal oxide field effect (MOSFET) which has a high resistance to electro-static discharge. The device has pre-gate heavily doped source and drain regions which overlap the gate electrode and the source and drain regions. This improved MOSFET device with overlapping pre-gate source and drain regions is incorporated into an electro-static discharge (ESD) circuit to form a memory device which has a high resistance to electro-static discharge (ESD).The MOSFET device with pre-gate heavily doped source and drain regions can be formed as follows. Spaced pre-gate source and drain regions of a second conductivity type are formed in the substrate with a background doping of a first conductivity type. A gate oxide and a gate is formed in the regions between the pre-gate source and drain regions. The gate at least partially overhangs the pre-gate source and drain regions. Subsequently, spacers are formed on the vertical sidewalls of the gate. Source and drain regions in the substrate are formed on either side of the spacers. Next, using conventional processes, insulating and metal layers are added to connect the circuit elements and form a memory device. The device is connected to form the input and input/output ESD circuits. The combination of the device of the invention and the ESD protection circuit forms an ESD resistant circuit using a minimum number of manufacturing steps.

Abstract translation: 改进了对静电放电具有高抗性的金属氧化物场效应（MOSFET）的制造结构和工艺。 该器件具有与栅电极和源极和漏极区重叠的预栅极重掺杂源极和漏极区。 这种具有重叠预栅极源极和漏极区域的改进的MOSFET器件被并入到静电放电（ESD）电路中，以形成具有高抗静电放电（ESD）的存储器件。 具有预栅极重掺杂源极和漏极区的MOSFET器件可以如下形成。 具有第二导电类型的间隔的预栅极源极和漏极区域形成在具有第一导电类型的背景掺杂的衬底中。 在栅极源极和漏极区域之间的区域中形成栅极氧化物和栅极。 栅极至少部分地悬垂在栅极之前的源极和漏极区域。 随后，在栅极的垂直侧壁上形成间隔物。 衬底中的源区和漏区形成在间隔物的两侧。 接下来，使用常规方法，添加绝缘和金属层以连接电路元件并形成存储器件。 该器件被连接以形成输入和输入/输出ESD电路。 本发明的器件与ESD保护电路的组合使用最少数量的制造步骤形成耐ESD电路。

公开(公告)号：US5567970A

公开(公告)日：1996-10-22

申请号：US430192

申请日：1995-04-27

Applicant: Shing-Ren Sheu ,  Chen-Chiu Hsue ,  Chen-Hui Chung

Inventor： Shing-Ren Sheu ,  Chen-Chiu Hsue ,  Chen-Hui Chung

IPC: H01L21/8246 ,  H01L27/112 ,  H01L29/78

CPC classification number: H01L27/1126 ,  H01L27/112

Abstract: A ROM device includes cells with buried bit lines in a semiconductor substrate. A thin insulating layer covers the substrate has closely spaced, parallel, word lines formed thereon arranged orthogonally relative to the bit lines. The word lines are covered with reflowed glass insulating layers about 2500.ANG. thick. The glass insulating layers comprise a sublayer of undoped glass and an overlayer of doped glass, the underlayer about 500.ANG.-1500.ANG. thick and the overlayer about 1000.ANG.-1500.ANG. thick. An etched, patterned metal layer is formed on the glass insulating layer. The overlayer has been substantially removed by etching where the metal layer has been etched. An ion implantation pattern has been implanted into the substrate adjacent to the conductive lines. The device has been passivated. The implanted impurity ions having been activated by annealing the device.

Abstract translation: ROM器件包括在半导体衬底中具有掩埋位线的单元。 覆盖衬底的薄绝缘层具有紧密间隔的平行的字线，其形成在其上相对于位线正交布置。 字线覆盖约2500 ANGSTROM厚的回流玻璃绝缘层。 玻璃绝缘层包括未掺杂玻璃的子层和掺杂玻璃的覆盖层，底层厚约为500，厚度约为1000。 在玻璃绝缘层上形成蚀刻图案化的金属层。 通过蚀刻已经基本上去除了覆盖层，其中金属层被蚀刻。 已经将离子注入图案植入到与导电线相邻的衬底中。 该设备已被钝化。 植入的杂质离子已经通过退火器件而被激活。