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    3-DIMENSIONAL INTEGRATED CIRCUIT DESIGNING METHOD
    12.
    发明申请
    3-DIMENSIONAL INTEGRATED CIRCUIT DESIGNING METHOD 失效
    三维集成电路设计方法

    公开(公告)号：US20100072614A1

    公开(公告)日：2010-03-25

    申请号：US12504272

    申请日：2009-07-16

    申请人： Shinobu Fujita

    发明人： Shinobu Fujita

    IPC分类号： H01L23/52 ,  G06F17/50

    CPC分类号： G06F17/5068 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A 3-dimensional integrated circuit designing method includes forming a temporary layout region for an original integrated circuit on an XY plane, the plane being short in an X direction and long in a Y direction perpendicular to the X direction, dividing the temporary layout region into 2N (N is an integral number of not smaller than 2) or more subregions in the Y direction, configuring one block for every successive N subregions to prepare a plurality of blocks, and forming N layers of layout by alternately folding each of the blocks in the Y direction in units of one subregion to selectively set a kN-th (k is an integral number not less than 1) subregion and (kN+1)th subregion of each block to one of an uppermost layer and lowermost layer.

    摘要翻译： 三维集成电路设计方法包括在XY平面上形成用于原始集成电路的临时布局区域，该平面在X方向上短并且在垂直于X方向的Y方向上长，将临时布局区域分成 2N（N是不小于2的整数）或更多个子区域，为每个连续的N个子区域配置一个块以准备多个块，并且通过交替地将每个块的每个块交替地折叠来形成N个层的布局 以一个子区域为单位的Y方向，选择性地将各块的kN（k为1以上的整数）子区域和（kN + 1）个子区域设置为最上层和最下层中的一个。

    RANDOM NUMBER GENERATION DEVICE
    14.
    发明申请
    RANDOM NUMBER GENERATION DEVICE 审中-公开
    随机数生成装置

    公开(公告)号：US20090309646A1

    公开(公告)日：2009-12-17

    申请号：US12391640

    申请日：2009-02-24

    申请人： Shigeki KOBAYASHI ,  Ken Uchida ,  Shinobu Fujita ,  Tetsufumi Tanamoto

    发明人： Shigeki KOBAYASHI ,  Ken Uchida ,  Shinobu Fujita ,  Tetsufumi Tanamoto

    IPC分类号： G06G7/12 ,  H01L27/088

    CPC分类号： H01L29/1054 ,  G06F7/588 ,  H01L21/823807 ,  H01L27/088 ,  H01L29/7843 ,  H03K3/84

    摘要： A random number generation device includes: a first source region; a first drain region; a first channel region provided between the first source region and the first drain region; a first insulating film provided on the first channel region; and a first gate electrode provided on the first insulating film. The first insulating film has a trap capturing and releasing a charge, and a tensile or compressive stress is applied in a direction of a gate length to at least one of the first channel region and the first insulating film.

    摘要翻译： 随机数生成装置包括：第一源区域; 第一漏区; 设置在所述第一源极区域和所述第一漏极区域之间的第一沟道区域; 设置在所述第一沟道区上的第一绝缘膜; 以及设置在第一绝缘膜上的第一栅电极。 第一绝缘膜具有陷阱捕获和释放电荷，并且在栅极长度方向上向第一沟道区和第一绝缘膜中的至少一个施加拉伸或压缩应力。

    RANDOM NUMBER GENERATING DEVICE
    16.
    发明申请
    RANDOM NUMBER GENERATING DEVICE 失效
    随机数生成装置

    公开(公告)号：US20080251783A1

    公开(公告)日：2008-10-16

    申请号：US12143124

    申请日：2008-06-20

    申请人： Tetsufumi TANAMOTO ,  Shinobu Fujita

    发明人： Tetsufumi TANAMOTO ,  Shinobu Fujita

    IPC分类号： H01L29/00

    CPC分类号： B82Y10/00 ,  G06F7/588 ,  H01L29/7888 ,  H04L9/0861

    摘要： The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel with each other, and a pair of first and second fine particles, which can mutually exchange charges, and are located in the vicinity of the first and second current paths.

    摘要翻译： 目的是提供具有较小的电路尺寸和较小的输出偏压值的随机数产生装置。 随机数产生装置包括彼此平行布置的一对第一和第二电流路径，以及一对可互相交换电荷并位于第一和第二电流路径附近的第一和第二细颗粒 。

    Random number generating circuit, semiconductor integrated circuit, IC card and information terminal device
    17.
    发明申请
    Random number generating circuit, semiconductor integrated circuit, IC card and information terminal device 有权
    随机数发生电路，半导体集成电路，IC卡和信息终端装置

    公开(公告)号：US20050108308A1

    公开(公告)日：2005-05-19

    申请号：US10919291

    申请日：2004-08-17

    申请人： Shinichi Yasuda ,  Shinobu Fujita

    发明人： Shinichi Yasuda ,  Shinobu Fujita

    IPC分类号： G06F7/58 ,  G09C1/00

    CPC分类号： G06F7/58

    摘要： A random number generating circuit receives as input a first digital random number signal generated at a first generating rate and produces as output a second digital random number signal having a second generating rate that is twice as high as the first generating rate. A semiconductor integrated circuit, an IC card and an information terminal device comprising the random number circuit is provided.

    摘要翻译： 随机数产生电路接收以第一产生速率产生的第一数字随机数信号作为输出，产生第二数字随机数信号，该第二数字随机数信号的第二发生速率是第一发生速率的两倍。 提供了包括随机数电路的半导体集成电路，IC卡和信息终端装置。

    Cache system and information-processing device
    18.
    发明授权
    Cache system and information-processing device 有权
    缓存系统和信息处理设备

    公开(公告)号：US08724403B2

    公开(公告)日：2014-05-13

    申请号：US13729382

    申请日：2012-12-28

    申请人： Kumiko Nomura ,  Shinobu Fujita ,  Keiko Abe ,  Kazutaka Ikegami ,  Hiroki Noguchi

    发明人： Kumiko Nomura ,  Shinobu Fujita ,  Keiko Abe ,  Kazutaka Ikegami ,  Hiroki Noguchi

    IPC分类号： G11C7/06

    CPC分类号： G06F1/3206 ,  G06F1/3225 ,  G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

    摘要： According to one embodiment, a cache system includes a tag memory includes a volatile memory device, the tag memory includes ways and storing a tag for each line, a data memory includes a nonvolatile memory device including sense amplifiers for reading data, the data memory includes ways and storing data for each line, a comparison circuit configured to compare a tag included in an address supplied from an external with a tag read from the tag memory, and a controller configured to turn off a power of a sense amplifier for a way which is not accessed based on a comparison result of the comparison circuit.

    摘要翻译： 根据一个实施例，缓存系统包括标签存储器，其包括易失性存储器设备，标签存储器包括每条线路的方式和存储标签，数据存储器包括包括用于读取数据的读出放大器的非易失性存储器件，数据存储器包括 方式和存储每行的数据，比较电路，被配置为将从外部提供的地址中包含的标签与从标签存储器读取的标签进行比较，以及控制器，被配置为关闭读出放大器的功率， 基于比较电路的比较结果不被访问。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    19.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
    半导体集成电路

    公开(公告)号：US20130307054A1

    公开(公告)日：2013-11-21

    申请号：US13606292

    申请日：2012-09-07

    申请人： Shinichi YASUDA ,  Kosuke Tatsumura ,  Mari Matsumoto ,  Koichiro Zaitsu ,  Masato Oda ,  Atsuhiro Kinoshita ,  Daisuke Hagishima ,  Yoshifumi Nishi ,  Takahiro Kurita ,  Shinobu Fujita

    发明人： Shinichi YASUDA ,  Kosuke Tatsumura ,  Mari Matsumoto ,  Koichiro Zaitsu ,  Masato Oda ,  Atsuhiro Kinoshita ,  Daisuke Hagishima ,  Yoshifumi Nishi ,  Takahiro Kurita ,  Shinobu Fujita

    IPC分类号： H01L27/105

    CPC分类号： G11C16/10 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/7881 ,  H01L29/792

    摘要： One embodiment provides a semiconductor integrated circuit, including: a substrate; a plurality of nonvolatile memory portions formed in the substrate, each including a first nonvolatile memory and a second nonvolatile memory; and a plurality of logic transistor portions formed in the substrate, each including at least one of logic transistor, wherein the logic transistors include: a first transistor which is directly connected to drains of the first and second nonvolatile memories at its gate; and a second transistor which is not directly connected to the drains of the first and second nonvolatile memories, and wherein a bottom surface of the gate of each of the logic transistors sandwiching the first and second nonvolatile memories is lower in height from a top surface of the substrate than a bottom surface of the control gate of each of the first and second nonvolatile memories.

    摘要翻译： 一个实施例提供一种半导体集成电路，包括：基板; 形成在所述基板中的多个非易失性存储部，每个包括第一非易失性存储器和第二非易失性存储器; 以及形成在所述衬底中的多个逻辑晶体管部分，每个逻辑晶体管部分包括逻辑晶体管中的至少一个，其中所述逻辑晶体管包括：第一晶体管，其第一和第二非易失性存储器的栅极直接连接到第一晶体管; 以及第二晶体管，其不直接连接到第一和第二非易失性存储器的漏极，并且其中夹着第一和第二非易失性存储器的每个逻辑晶体管的栅极的底表面的高度与 所述基板比所述第一和第二非易失性存储器中的每一个的所述控制栅极的底表面。