公开(公告)号：US20130330883A1

公开(公告)日：2013-12-12

申请号：US13964465

申请日：2013-08-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Jung-Pang Huang ,  Hui-Min Huang ,  Kuan-Wei Chuang ,  Chun-Tang Lin ,  Yih-Jenn Jiang

IPC: H01L21/56

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/014 ,  H01L2924/3511

Abstract: A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.

Abstract translation: 半导体封装包括：具有多个电极焊盘的有源表面和与该有源表面相对的无效表面的芯片; 密封剂，其封装所述芯片并且具有相对的第一和第二表面，所述第一表面与所述芯片的有源表面齐平; 以及形成在密封剂的第二表面上的第一和第二金属层，由此为整个结构提供刚性支撑以防止翘曲并促进整体结构的散热。

公开(公告)号：US09899237B2

公开(公告)日：2018-02-20

申请号：US14174988

申请日：2014-02-07

Applicant: Siliconware Precision Industries Co., Ltd

Inventor： Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/673 ,  H01L21/768 ,  H01L21/78 ,  H01L21/68 ,  H01L21/48 ,  H01L21/683 ,  H01L21/677

CPC classification number: H01L21/56 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L21/673 ,  H01L21/67333 ,  H01L21/67763 ,  H01L21/68 ,  H01L21/683 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3121 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/1815 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

Abstract: A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.

公开(公告)号：US20170229364A1

公开(公告)日：2017-08-10

申请号：US15497964

申请日：2017-04-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/29 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2924/014 ,  H01L2924/00

Abstract: A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs.

公开(公告)号：US09117698B2

公开(公告)日：2015-08-25

申请号：US14449278

申请日：2014-08-01

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Jung-Pang Huang ,  Hsin-Yi Liao ,  Shih-Kuang Chiu ,  Guang-Hwa Ma

IPC: H01L21/56 ,  H01L23/48 ,  H01L21/02 ,  H01L21/50 ,  H01L29/84 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H01L23/538

CPC classification number: H01L24/11 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/19 ,  H01L24/24 ,  H01L24/81 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/033 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/1412 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/48227 ,  H01L2224/81 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost.

Abstract translation: 半导体封装包括：具有相反的第一和第二表面的电介质层; 嵌入在介电层中并具有多个电极焊盘的半导体芯片; 分别设置在半导体芯片的电极焊盘上的多个第一金属柱，使得第一金属柱的顶端从第一表面露出; 至少第二金属柱穿透介电层，使得第二金属柱的两个相对端分别从第一表面和第二表面露出; 第一电路层，形成在第一表面上，用于电连接第一和第二金属柱; 以及形成在所述第二表面上用于电连接所述第二金属柱的第二电路层。 该半导体封装省去了用于在模塑料中形成导电柱的常规激光烧蚀和电镀工艺，从而节省制造时间和成本。

公开(公告)号：US20140342507A1

公开(公告)日：2014-11-20

申请号：US14449278

申请日：2014-08-01

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Jung-Pang Huang ,  Hsin-Yi Liao ,  Shih-Kuang Chiu ,  Guang-Hwa Ma

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/19 ,  H01L24/24 ,  H01L24/81 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/033 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/1412 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/48227 ,  H01L2224/81 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost.

Abstract translation: 半导体封装包括：具有相反的第一和第二表面的电介质层; 嵌入在介电层中并具有多个电极焊盘的半导体芯片; 分别设置在半导体芯片的电极焊盘上的多个第一金属柱，使得第一金属柱的顶端从第一表面露出; 至少第二金属柱穿透介电层，使得第二金属柱的两个相对端分别从第一表面和第二表面露出; 第一电路层，形成在第一表面上，用于电连接第一和第二金属柱; 以及形成在所述第二表面上用于电连接所述第二金属柱的第二电路层。 该半导体封装省去了用于在模塑料中形成导电柱的常规激光烧蚀和电镀工艺，从而节省制造时间和成本。

公开(公告)号：US20140021629A1

公开(公告)日：2014-01-23

申请号：US13654754

申请日：2012-10-18

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu ,  Fu-Tang Huang

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/96 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/24153 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.

Abstract translation: 提供一种制造半导体封装的方法，包括：通过粘合剂层将多个半导体元件设置在载体上，使载体的一部分从粘合剂层露出; 形成密封剂以封装半导体元件; 去除粘合剂层和载体以暴露半导体元件; 以及在半导体元件上形成积聚结构。 由于当温度变化时粘合剂层被分成多个不会由于膨胀或收缩而相互影响的分离部分，所以本发明防止了半导体元件在成型过程中的位置偏差，从而提高了对准精度。