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11.发明授权Methods of forming transistor devices with high-k insulation layers and the resulting devices 有权形成具有高k绝缘层的晶体管器件和所产生的器件的方法公开(公告)号：US09136177B2
公开(公告)日：2015-09-15
申请号：US13561315
申请日：2012-07-30
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L21/3205 , H01L21/4763 , H01L21/8234 , H01L21/8238 , H01L21/28 , H01L29/51 , H01L29/66 , H01L29/78
CPC分类号： H01L27/088 , H01L21/28202 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L29/42364 , H01L29/42376 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/7833
摘要： Method of forming transistor devices is disclosed that includes forming a first layer of high-k insulating material and a sacrificial protection layer above first and second active regions, removing the first layer of insulating material and the protection layer from above the second active region, removing the protection layer from above the first layer of insulating material positioned above the first active region, forming a second layer of high-k insulating material above the first layer of insulating material and the second active region, forming a layer of metal above the second layer of insulating material, and removing portions of the first and second layers of insulating material and the metal layer to form a first gate stack (comprised of the first and second layers of high-k material and the layer of metal) and a second gate stack (comprised of the second layer of high-k material and the layer of metal).
摘要翻译： 公开了形成晶体管器件的方法，其包括在第一和第二有源区之上形成第一层高k绝缘材料和牺牲保护层，从第二有源区上方去除第一绝缘材料层和保护层，去除 所述保护层位于所述第一绝缘材料层上方，位于所述第一有源区上方，在所述第一绝缘材料层和所述第二有源区上方形成第二层高k绝缘材料，在所述第二层上方形成金属层 的绝缘材料，并且去除第一和第二绝缘材料层和金属层的部分以形成第一栅极叠层（由第一和第二层高k材料和金属层组成）和第二栅极堆叠 （由第二层高k材料和金属层组成）。
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12.发明申请INTEGRATED CIRCUITS HAVING BORON-DOPED SILICON GERMANIUM CHANNELS AND METHODS FOR FABRICATING THE SAME 审中-公开具有硼掺杂硅锗通道的集成电路及其制造方法公开(公告)号：US20140070321A1
公开(公告)日：2014-03-13
申请号：US13613190
申请日：2012-09-13
IPC分类号： H01L27/088 , H01L21/20
CPC分类号： H01L21/823807 , H01L21/823878 , H01L29/1054 , H01L29/4966 , H01L29/51 , H01L29/66651 , H01L29/7833
摘要： Integrated circuits and methods for fabricating integrated circuits are provided. One method includes recessing a PFET active region to form a recessed PFET surface region. A boron-doped SiGe channel is formed overlying the recessed PFET surface region.
摘要翻译： 提供了用于制造集成电路的集成电路和方法。 一种方法包括凹陷PFET有源区以形成凹陷的PFET表面区域。 在凹陷的PFET表面区域上形成掺杂硼的SiGe沟道。
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13.发明申请METHODS OF FORMING TRANSISTOR DEVICES WITH HIGH-K INSULATION LAYERS AND THE RESULTING DEVICES 有权用高K绝缘层和结晶器件形成晶体管器件的方法公开(公告)号：US20140027859A1
公开(公告)日：2014-01-30
申请号：US13561315
申请日：2012-07-30
IPC分类号： H01L21/28 , H01L27/088
CPC分类号： H01L27/088 , H01L21/28202 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L29/42364 , H01L29/42376 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/7833
摘要： Method of forming transistor devices is disclosed that includes forming a first layer of high-k insulating material and a sacrificial protection layer above first and second active regions, removing the first layer of insulating material and the protection layer from above the second active region, removing the protection layer from above the first layer of insulating material positioned above the first active region, forming a second layer of high-k insulating material above the first layer of insulating material and the second active region, forming a layer of metal above the second layer of insulating material, and removing portions of the first and second layers of insulating material and the metal layer to form a first gate stack (comprised of the first and second layers of high-k material and the layer of metal) and a second gate stack (comprised of the second layer of high-k material and the layer of metal).
摘要翻译： 公开了形成晶体管器件的方法，其包括在第一和第二有源区之上形成第一层高k绝缘材料和牺牲保护层，从第二有源区上方去除第一绝缘材料层和保护层，去除 所述保护层位于所述第一绝缘材料层上方，位于所述第一有源区上方，在所述第一绝缘材料层和所述第二有源区上方形成第二层高k绝缘材料，在所述第二层上方形成金属层 的绝缘材料，并且去除第一和第二绝缘材料层和金属层的部分以形成第一栅极叠层（由第一和第二层高k材料和金属层组成）和第二栅极堆叠 （由第二层高k材料和金属层组成）。
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14.发明授权Shallow source and drain architecture in an active region of a semiconductor device having a pronounced surface topography by tilted implantation 有权通过倾斜植入具有显着表面形貌的半导体器件的有源区域中的浅源极和漏极结构公开(公告)号：US08614134B2
公开(公告)日：2013-12-24
申请号：US13052583
申请日：2011-03-21
申请人： Martin Gerhardt , Peter Javorka , Juergen Faul
发明人： Martin Gerhardt , Peter Javorka , Juergen Faul
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L21/26586 , H01L21/28518 , H01L21/76897 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： In sophisticated semiconductor devices, a shallow drain and source concentration profile may be obtained for active regions having a pronounced surface topography by performing tilted implantation steps upon incorporating the drain and source dopant species. In this manner, a metal silicide may be reliably embedded in the drain and source regions.
摘要翻译： 在复杂的半导体器件中，通过在掺入漏极和源极掺杂剂物质时执行倾斜的注入步骤，可以获得具有显着表面形貌的有源区域的浅漏极和源极浓度分布。 以这种方式，金属硅化物可以可靠地嵌入漏极和源极区域中。
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15.发明申请Method for Forming a Strained Transistor by Stress Memorization Based on a Stressed Implantation Mask 审中-公开基于强迫植入面膜的应力记忆形成应变晶体管的方法公开(公告)号：US20110223733A1
公开(公告)日：2011-09-15
申请号：US13108087
申请日：2011-05-16
申请人： Frank Wirbeleit , Roman Boschke , Martin Gerhardt
发明人： Frank Wirbeleit , Roman Boschke , Martin Gerhardt
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/26513 , H01L21/266 , H01L21/324 , H01L21/7624 , H01L29/6656 , H01L29/6659 , H01L29/7843
摘要： By using an implantation mask having a high intrinsic stress, SMT sequences may be provided in which additional lithography steps may be avoided. Consequently, a strain source may be provided without significantly contributing to the overall process complexity.
摘要翻译： 通过使用具有高固有应力的注入掩模，可以提供SMT序列，其中可以避免额外的光刻步骤。 因此，可以提供应变源而不显着地有助于整个工艺的复杂性。
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16.发明申请TECHNIQUE FOR STRAIN ENGINEERING IN SILICON-BASED TRANSISTORS BY USING IMPLANTATION TECHNIQUES FOR FORMING A STRAIN-INDUCING LAYER UNDER THE CHANNEL REGION 有权通过使用在通道区域形成应变诱导层的植入技术在硅基晶体管中进行菌株工程的技术公开(公告)号：US20080296692A1
公开(公告)日：2008-12-04
申请号：US12015692
申请日：2008-01-17
申请人： Uwe Griebenow , Kai Frohberg , Martin Gerhardt
发明人： Uwe Griebenow , Kai Frohberg , Martin Gerhardt
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823814 , H01L27/092 , H01L29/1054
摘要： By incorporating a semiconductor species having the same valence and a different covalent radius compared to the base semiconductor material on the basis of an ion implantation process, a strain-inducing material may be positioned locally within a transistor at an appropriate manufacturing stage, thereby substantially not contributing to overall process complexity and also not affecting the further processing of the semiconductor device. Hence, a high degree of flexibility may be provided with respect to enhancing transistor performance in a highly local manner.
摘要翻译： 通过在离子注入工艺的基础上结合具有与基底半导体材料相比具有相同价态和不同共价半径的半导体物质，应变诱导材料可以在适当的制造阶段局部地定位在晶体管内，从而基本上不 有助于整个过程的复杂性，也不影响半导体器件的进一步处理。 因此，可以以高度局部的方式提高晶体管性能方面的高度的灵活性。
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17.发明申请METHOD OF INCREASING TRANSISTOR DRIVE CURRENT BY RECESSING AN ISOLATION TRENCH 有权通过记录隔离开关增加晶体管驱动电流的方法公开(公告)号：US20070278596A1
公开(公告)日：2007-12-06
申请号：US11620406
申请日：2007-01-05
CPC分类号： H01L21/76224 , H01L29/665
摘要： By recessing the isolation structure of a transistor prior to silicidation, the series resistance may be reduced due to the increased amount of metal silicide formed in the vicinity of the isolation structure. By recessing the isolation structure prior to the formation of the gate electrode, an increased degree of poly wrap around may be obtained, thereby increasing the effective channel width.
摘要翻译： 通过在硅化之前使晶体管的隔离结构凹陷，由于在隔离结构附近形成的金属硅化物的量增加，串联电阻可能会降低。 通过在形成栅电极之前使隔离结构凹陷，可以获得增加的聚环绕的程度，从而增加有效沟道宽度。
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18.发明申请Shallow Source and Drain Architecture in an Active Region of a Semiconductor Device Having a Pronounced Surface Topography by Tilted Implantation 有权通过倾斜植入具有广泛表面形貌的半导体器件的有源区域中的浅源和漏极结构公开(公告)号：US20120241864A1
公开(公告)日：2012-09-27
申请号：US13052583
申请日：2011-03-21
申请人： Martin Gerhardt , Peter Javorka , Juergen Faul
发明人： Martin Gerhardt , Peter Javorka , Juergen Faul
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/26586 , H01L21/28518 , H01L21/76897 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： In sophisticated semiconductor devices, a shallow drain and source concentration profile may be obtained for active regions having a pronounced surface topography by performing tilted implantation steps upon incorporating the drain and source dopant species. In this manner, a metal silicide may be reliably embedded in the drain and source regions.
摘要翻译： 在复杂的半导体器件中，通过在掺入漏极和源极掺杂剂物质时执行倾斜的注入步骤，可以获得具有显着表面形貌的有源区域的浅漏极和源极浓度分布。 以这种方式，金属硅化物可以可靠地嵌入漏极和源极区域中。
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19.发明授权Method of enhancing lithography capabilities during gate formation in semiconductors having a pronounced surface topography 有权在具有明显的表面形貌的半导体中增强栅极形成期间光刻能力的方法公开(公告)号：US08101512B2
公开(公告)日：2012-01-24
申请号：US11773631
申请日：2007-07-05
IPC分类号： H01L21/4763
CPC分类号： H01L21/28123 , H01L29/66772
摘要： In a mesa isolation configuration for forming a transistor on a semiconductor island, an additional planarization step is performed to enhance the uniformity of the gate patterning process. In some illustrative embodiments, the gate electrode material may be planarized, for instance, on the basis of CMP, to compensate for the highly non-uniform surface topography, when the gate electrode material is formed above the non-filled isolation trenches. Consequently, significant advantages of the mesa isolation strategy may be combined with a high degree of scalability due to the enhancement of the critical gate patterning process.
摘要翻译： 在用于在半导体岛上形成晶体管的台面隔离结构中，执行附加的平面化步骤以增强栅极图案化工艺的均匀性。 在一些说明性实施例中，当栅电极材料形成在未填充的隔离沟槽上方时，栅电极材料可以例如基于CMP平坦化，以补偿高度不均匀的表面形貌。 因此，由于关键栅极图案化工艺的增强，台面隔离策略的显着优点可能与高度可扩展性相结合。
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20.发明申请ENHANCED STRESS TRANSFER IN AN INTERLAYER DIELECTRIC BY USING AN ADDITIONAL STRESS LAYER ABOVE A DUAL STRESS LINER IN A SEMICONDUCTOR DEVICE 有权通过在半导体器件中使用双应力衬垫上的附加应力层在中间层介质中增强应力传递公开(公告)号：US20080179661A1
公开(公告)日：2008-07-31
申请号：US11865796
申请日：2007-10-02
申请人： Ralf Richter , Martin Gerhardt , Martin Mazur , Joerg Hohage
发明人： Ralf Richter , Martin Gerhardt , Martin Mazur , Joerg Hohage
IPC分类号： H01L29/78 , H01L21/469
CPC分类号： H01L29/7833 , H01L21/76802 , H01L21/76825 , H01L21/76832 , H01L21/76837 , H01L21/823412 , H01L21/823807 , H01L27/092 , H01L29/7843
摘要： By forming an additional stressed dielectric material after patterning dielectric liners of different intrinsic stress, a significant increase of performance in transistors may be obtained while substantially not contributing to patterning non-uniformities during the formation of respective contact openings in highly scaled semiconductor devices. The additional dielectric layer may be provided with any type of intrinsic stress, irrespective of the previously selected patterning sequence.
摘要翻译： 通过在对具有不同的本征应力的介电衬垫进行图案化之后形成附加的应力介电材料，可以获得在晶体管中性能的显着提高，同时在高比例尺度的半导体器件中形成各个接触开口期间基本上不会构图不均匀性。 附加介电层可以被提供任何类型的固有应力，而不管先前选择的图案化序列如何。
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