利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

206 条记录 (耗时 0.027 秒)

    FPGA with a plurality of I/O voltage levels
    11.
    发明授权
    FPGA with a plurality of I/O voltage levels 有权
    具有多个I / O电压电平的FPGA

    公开(公告)号：US6049227A

    公开(公告)日：2000-04-11

    申请号：US187666

    申请日：1998-11-05

    申请人： F. Erich Goetting ,  Scott O. Frake ,  Venu M. Kondapalli ,  Steven P. Young

    发明人： F. Erich Goetting ,  Scott O. Frake ,  Venu M. Kondapalli ,  Steven P. Young

    IPC分类号： G06F7/38 ,  H03K19/003 ,  H03K19/094 ,  H03K19/177 ,  H03K19/0175 ,  H03K19/082

    CPC分类号： H03K19/17744 ,  H03K19/00361 ,  H03K19/1778 ,  H03K19/17788

    摘要： The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.

    摘要翻译： 本发明包括具有多个输入参考电压和/或输出电压源的FPGA。 在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。 根据本发明的第二方面，I / O焊盘线可配置地连接到输入参考电压线，使得可以使用任何可配置的输入/输出块（IOB）来提供输入参考电压。 根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。 根据本发明的另一方面，将单个输入参考电压和/或单个输出电压电源应用于每个IOB，其中IOB被分组成组。 每组IOB具有单独的输入参考电压和/或单独的输出电压电源。

    Structures and methods to avoiding hold time violations in a programmable logic device
    13.
    发明授权
    Structures and methods to avoiding hold time violations in a programmable logic device 有权
    避免可编程逻辑器件中的保持时间违规的结构和方法

    公开(公告)号：US07548089B1

    公开(公告)日：2009-06-16

    申请号：US11880724

    申请日：2007-07-24

    申请人： Trevor J. Bauer ,  Ramakrishna K. Tanikella ,  Steven P. Young

    发明人： Trevor J. Bauer ,  Ramakrishna K. Tanikella ,  Steven P. Young

    IPC分类号： H01L25/00

    CPC分类号： H03K19/17736 ,  H03K19/00323

    摘要： Structures and methods of avoiding hold time violations in a design implemented in a PLD. In a programmable device, the delay of a signal path varies, e.g., depending on the separation between the source and destination of the signal. An optional delay element is provided between a programmable interconnect structure and a destination logic element having a clock skew relative to the source. The optional delay element is programmed by the implementation software to introduce a delay on the signal path when necessary to meet the hold time requirements for the destination logic element. The optional delay is designed to be large enough to overcome hold-time violations even for the largest possible clock skew and the smallest possible signal delay. When no hold time violation occurs, the optional delay element is configured to bypass the additional delay, to avoid imposing a large setup requirement on the signal.

    摘要翻译： 在PLD中实现的设计中避免持续时间违规的结构和方法。 在可编程设备中，信号路径的延迟例如取决于信号的源和目的地之间的间隔而变化。 在可编程互连结构和具有相对于源的时钟偏移的目的地逻辑元件之间提供可选的延迟元件。 可选延迟元件由实现软件编程，以在必要时在信号路径上引入延迟以满足目的地逻辑元件的保持时间要求。 可选延迟被设计为足够大，以克服即使对于最大可能的时钟偏移和尽可能小的信号延迟的保持时间违规。 当没有发生保持时间违规时，可选的延迟元件被配置为绕过附加延迟，以避免对信号施加大的设置要求。

    Programmable integrated circuit with mirrored interconnect structure
    14.
    发明授权
    Programmable integrated circuit with mirrored interconnect structure 有权
    具有镜像互连结构的可编程集成电路

    公开(公告)号：US08120382B2

    公开(公告)日：2012-02-21

    申请号：US12718848

    申请日：2010-03-05

    申请人： Trevor J. Bauer ,  Ramakrishna K. Tanikella ,  Steven P. Young

    发明人： Trevor J. Bauer ,  Ramakrishna K. Tanikella ,  Steven P. Young

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17796

    摘要： A programmable integrated circuit (IC) with mirrored interconnect structure. The IC includes a plurality of arrangements, which are horizontally arranged. Each arrangement includes a first logic column, an interconnect column, and a second logic column. Each interconnect column includes programmable interconnect blocks (148), and each of the first and second logic columns includes programmable logic blocks. Each programmable interconnect block provides a plurality of first input and output ports on a first side and a plurality of second input and output ports on a second side. The first ports and the first side of each of the programmable interconnect blocks physically mirror the second ports and the second side of the programmable interconnect block. The ports of the programmable interconnect blocks are coupled to the ports of the programmable logic blocks in the first and second logic columns.

    摘要翻译： 具有镜像互连结构的可编程集成电路（IC）。 IC包括水平布置的多个布置。 每个布置包括第一逻辑列，互连列和第二逻辑列。 每个互连列包括可编程互连块（148），并且第一和第二逻辑列中的每一个包括可编程逻辑块。 每个可编程互连块在第一侧上提供多个第一输入和输出端口以及在第二侧上提供多个第二输入和输出端口。 每个可编程互连块的第一端口和第一侧物理地镜像可编程互连块的第二端口和第二侧。 可编程互连块的端口耦合到第一和第二逻辑列中的可编程逻辑块的端口。

    Integrated circuit interconnect structure having reduced coupling between interconnect lines
    15.
    发明授权
    Integrated circuit interconnect structure having reduced coupling between interconnect lines 有权
    集成电路互连结构具有减少互连线之间的耦合

    公开(公告)号：US07199610B1

    公开(公告)日：2007-04-03

    申请号：US11152360

    申请日：2005-06-14

    申请人： Steven P. Young ,  Ramakrishna K. Tanikella ,  Sanjiv Stokes

    发明人： Steven P. Young ,  Ramakrishna K. Tanikella ,  Sanjiv Stokes

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736

    摘要： An interconnect structure in which “diagonal” and “straight” interconnect lines are interleaved to minimize coupling between adjacent interconnect lines. An interconnect structure for an integrated circuit comprises rows and columns of tiles. Interconnect lines extend at least in part along a first column of the tiles, the interconnect lines including straight and diagonal interconnect lines. A “straight” interconnect line interconnects at least two tiles in the first column, and a “diagonal” interconnect line interconnects a tile in the first column with at least one tile in a different column and row. The interconnect lines are laid out in parallel fashion such that no straight interconnect line is physically adjacent to more than one other straight interconnect line, and no diagonal interconnect line is physically adjacent to more than one other diagonal interconnect line. Optionally, no two physically adjacent interconnect lines drive in the same direction within the first column.

    摘要翻译： 互连结构，其中“对角线”和“直”互连线被交织以最小化相邻互连线之间的耦合。 用于集成电路的互连结构包括行和列的瓦片。 互连线至少部分地沿着瓦片的第一列延伸，所述互连线包括直线和对角互连线。 “直”互连线将第一列中的至少两个瓦片互连，并且“对角线”互连线将第一列中的瓦片与不同列和行中的至少一个瓦片互连。 互连线以平行的方式布置，使得没有直线互连线在物理上与多于另一条直的互连线相邻，并且对角互连线在物理上与多于一个其它对角线互连线相邻。 可选地，没有两个物理上相邻的互连线在第一列内沿相同的方向驱动。

    PLD lookup table including transistors of more than one oxide thickness
    16.
    发明授权
    PLD lookup table including transistors of more than one oxide thickness 有权
    PLD查找表包括多于一个氧化物厚度的晶体管

    公开(公告)号：US07053654B1

    公开(公告)日：2006-05-30

    申请号：US10869139

    申请日：2004-06-15

    申请人： Steven P. Young ,  Venu M. Kondapalli ,  Martin L. Voogel

    发明人： Steven P. Young ,  Venu M. Kondapalli ,  Martin L. Voogel

    IPC分类号： G06F7/38

    CPC分类号： H03K19/1778 ,  H03K19/1737 ,  H03K19/17728

    摘要： A structure that can be used, for example, to implement a lookup table for a programmable logic device (PLD). The structure includes configuration memory cells, pass transistors, and a buffer. The pass transistors pass the output of a selected configuration memory cell to the buffer, and are controlled by data input signals of the structure. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The memory cells and buffer include transistors having a second oxide thickness thinner than the first oxide thickness, and operate at a second operating voltage lower than the first operating voltage. The data input signals are provided at the first operating voltage. Some embodiments include data generating circuits that include transistors having the first oxide thickness. Gate lengths can also vary between the memory cell transistors, pass transistors, buffer transistors, and data generating circuits.

    摘要翻译： 可用于例如实现可编程逻辑器件（PLD）的查找表的结构。 该结构包括配置存储单元，传输晶体管和缓冲器。 传输晶体管将所选配置存储单元的输出传递到缓冲器，并由结构的数据输入信号控制。 传输晶体管具有第一氧化物厚度并且由具有第一工作电压的值控制。 存储单元和缓冲器包括具有比第一氧化物厚度薄的第二氧化物厚度的晶体管，并且在低于第一工作电压的第二工作电压下工作。 在第一工作电压下提供数据输入信号。 一些实施例包括包括具有第一氧化物厚度的晶体管的数据产生电路。 栅极长度也可以在存储单元晶体管，传输晶体管，缓冲晶体管和数据产生电路之间变化。

    Integrated circuit multiplexer including transistors of more than one oxide thickness
    17.
    发明授权
    Integrated circuit multiplexer including transistors of more than one oxide thickness 有权
    集成电路多路复用器包括多于一个氧化物厚度的晶体管

    公开(公告)号：US06768335B1

    公开(公告)日：2004-07-27

    申请号：US10354520

    申请日：2003-01-30

    申请人： Steven P. Young ,  Michael J. Hart ,  Venu M. Kondapalli ,  Martin L. Voogel

    发明人： Steven P. Young ,  Michael J. Hart ,  Venu M. Kondapalli ,  Martin L. Voogel

    IPC分类号： G06F738

    CPC分类号： H03K17/005 ,  H03K17/693 ,  H03K19/17736 ,  H03K19/1778

    摘要： A multiplexer that can be used, for example, in a programmable logic device (PLD). The multiplexer includes a plurality of pass transistors passing a selected one of several input values to an internal node, which drives a buffer that provides the multiplexer output signal. The pass transistors can be controlled, for example, by values stored in memory cells of a PLD. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The buffer includes transistors having a second and thinner oxide thickness, and is operated at a second and lower operating voltage. Where memory cells are used to control the pass transistors, the memory cells include transistors having the first oxide thickness and operate at the first operating voltage. Some embodiments also include transistors of varying gate length for each of the pass transistors, buffer transistors, and memory cell transistors.

    摘要翻译： 可以用于例如可编程逻辑器件（PLD）中的多路复用器。 多路复用器包括将多个输入值中选择的一个输入值传送到内部节点的多个传输晶体管，驱动提供多路复用器输出信号的缓冲器。 可以例如通过存储在PLD的存储器单元中的值来控制传输晶体管。 传输晶体管具有第一氧化物厚度并且由具有第一工作电压的值控制。 缓冲器包括具有第二和较薄氧化物厚度的晶体管，并且在第二和较低工作电压下操作。 在使用存储器单元来控制传输晶体管的情况下，存储单元包括具有第一氧化物厚度并在第一工作电压下工作的晶体管。 一些实施例还包括用于每个传输晶体管，缓冲晶体管和存储单元晶体管的栅极长度变化的晶体管。

    FPGA with a plurality of input reference voltage levels grouped into sets
    18.
    发明授权
    FPGA with a plurality of input reference voltage levels grouped into sets 有权
    FPGA具有多个输入参考电压电平分组成组

    公开(公告)号：US06204691B1

    公开(公告)日：2001-03-20

    申请号：US09569745

    申请日：2000-05-11

    申请人： F. Erich Goetting ,  Scott O. Frake ,  Venu M. Kondapalli ,  Steven P. Young

    发明人： F. Erich Goetting ,  Scott O. Frake ,  Venu M. Kondapalli ,  Steven P. Young

    IPC分类号： H03K19094

    CPC分类号： H03K19/17744 ,  H03K19/00361 ,  H03K19/1778 ,  H03K19/17788

    摘要： The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.

    摘要翻译： 本发明包括具有多个输入参考电压和/或输出电压源的FPGA。 在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。 根据本发明的第二方面，I / O焊盘线可配置地连接到输入参考电压线，使得可以使用任何可配置的输入/输出块（IOB）来提供输入参考电压。 根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。 根据本发明的另一方面，将单个输入参考电压和/或单个输出电压电源应用于每个IOB，其中IOB被分组成组。 每组IOB具有单独的输入参考电压和/或单独的输出电压电源。

    Structures and methods for avoiding hold time violations in a programmable logic device
    19.
    发明授权
    Structures and methods for avoiding hold time violations in a programmable logic device 有权
    用于避免可编程逻辑器件中的保持时间违规的结构和方法

    公开(公告)号：US07312631B1

    公开(公告)日：2007-12-25

    申请号：US11264405

    申请日：2005-11-01

    申请人： Trevor J. Bauer ,  Ramakrishna K. Tanikella ,  Steven P. Young

    发明人： Trevor J. Bauer ,  Ramakrishna K. Tanikella ,  Steven P. Young

    IPC分类号： H03K19/177 ,  H03K19/173 ,  H03K19/00

    CPC分类号： H03K19/17736 ,  H03K19/00323

    摘要： Structures and methods of avoiding hold time violations in a design implemented in a PLD. In a programmable device, the delay of a signal path varies, e.g., depending on the separation between the source and destination of the signal. An optional delay element is provided between a programmable interconnect structure and a destination logic element having a clock skew relative to the source. The optional delay element is programmed by the implementation software to introduce a delay on the signal path when necessary to meet the hold time requirements for the destination logic element. The optional delay is designed to be large enough to overcome hold-time violations even for the largest possible clock skew and the smallest possible signal delay. When no hold time violation occurs, the optional delay element is configured to bypass the additional delay, to avoid imposing a large setup requirement on the signal.

    摘要翻译： 在PLD中实现的设计中避免持续时间违规的结构和方法。 在可编程设备中，信号路径的延迟例如取决于信号的源和目的地之间的间隔而变化。 在可编程互连结构和具有相对于源的时钟偏移的目的地逻辑元件之间提供可选的延迟元件。 可选延迟元件由实现软件编程，以在必要时在信号路径上引入延迟以满足目的地逻辑元件的保持时间要求。 可选延迟被设计为足够大，以克服即使对于最大可能的时钟偏移和尽可能小的信号延迟的保持时间违规。 当没有发生保持时间违规时，可选的延迟元件被配置为绕过附加延迟，以避免对信号施加大的设置要求。

    Structures and methods of testing interconnect structures in programmable logic devices
    20.
    发明授权
    Structures and methods of testing interconnect structures in programmable logic devices 有权
    在可编程逻辑器件中测试互连结构的结构和方法

    公开(公告)号：US06933747B1

    公开(公告)日：2005-08-23

    申请号：US10684183

    申请日：2003-10-10

    申请人： Trevor J. Bauer ,  Steven P. Young ,  Ramakrishna K. Tanikella

    发明人： Trevor J. Bauer ,  Steven P. Young ,  Ramakrishna K. Tanikella

    IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/17764 ,  G01R31/2853 ,  G01R31/31723 ,  G01R31/318516 ,  H03K19/17736

    摘要： Structures enabling the efficient testing of interconnect in programmable logic devices (PLDS), and methods utilizing these structures. A PLD includes a non-homogeneous array of programmable logic blocks and an array of standardized interconnect blocks, where the same interconnect block is used for different types of logic blocks. Coupled between each of the interconnect blocks and the associated logic block is a standardized test structure, allowing the same test configuration to be used for each interconnect block even though the interconnect blocks are associated with logic blocks of different types. In some embodiments, one or more types of logic blocks are not associated with standardized test structures. These logic blocks are coupled directly to their associated interconnect blocks, and are preferably of a type that can be configured to emulate the standardized test structure. Thus, by a correct application of configuration data all of the interconnect blocks display the same behavior.

    摘要翻译： 能够对可编程逻辑器件（PLDS）中的互连进行有效测试的结构以及利用这些结构的方法。 PLD包括可编程逻辑块的非均匀阵列和标准化互连块阵列，其中相同的互连块用于不同类型的逻辑块。 在每个互连块和相关联的逻辑块之间耦合是标准化的测试结构，允许将相同的测试配置用于每个互连块，即使互连块与不同类型的逻辑块相关联。 在一些实施例中，一个或多个类型的逻辑块不与标准化测试结构相关联。 这些逻辑块直接耦合到它们相关联的互连块，并且优选地是可被配置为模拟标准化测试结构的类型。 因此，通过配置数据的正确应用，所有互连块都显示相同的行为。