公开(公告)号：US20220199643A1

公开(公告)日：2022-06-23

申请号：US17690943

申请日：2022-03-09

Applicant: SunRise Memory Corporation

Inventor： Eli Harari ,  Scott Brad Herner ,  Wu-Yi Henry Chien

IPC: H01L27/11582 ,  H01L21/768 ,  H01L23/00 ,  H01L27/11578

Abstract: A method addresses low cost, low resistance metal interconnects and mechanical stability in a high aspect ratio structure. According to the various implementations disclosed herein, a replacement metal process, which defers the need for a metal etching step in the fabrication process until after all patterned photoresist is no longer present. Under this process, the conductive sublayers may be both thick and numerous. The present invention also provides for a strut structure which facilitates etching steps on high aspect ratio structures, which enhances mechanical stability in a high aspect ratio memory stack.

公开(公告)号：US11309331B2

公开(公告)日：2022-04-19

申请号：US17011836

申请日：2020-09-03

Applicant: Sunrise Memory Corporation

Inventor： Eli Harari ,  Scott Brad Herner ,  Wu-Yi Henry Chien

IPC: H01L21/00 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/00 ,  H01L27/11578 ,  H01L21/311 ,  G11C16/04

Abstract: A method addresses low cost, low resistance metal interconnects and mechanical stability in a high aspect ratio structure. According to the various implementations disclosed herein, a replacement metal process, which defers the need for a metal etching step in the fabrication process until after all patterned photoresist is no longer present. Under this process, the conductive sublayers may be both thick and numerous. The present invention also provides for a strut structure which facilitates etching steps on high aspect ratio structures, which enhances mechanical stability in a high aspect ratio memory stack.

公开(公告)号：US20210013224A1

公开(公告)日：2021-01-14

申请号：US16924531

申请日：2020-07-09

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Vinod Purayath ,  Wu-Yi Henry Chien

IPC: H01L27/11578 ,  H01L27/11565 ,  H01L27/11568 ,  H01L21/28 ,  H01L21/768 ,  H01L29/66 ,  H01L29/792

Abstract: In the highly efficient fabrication processes for HNOR arrays provided herein, the channel regions of the storage transistors in the HNOR arrays are protected by a protective layer after deposition until the subsequent deposition of a charge-trapping material before forming local word lines. Both the silicon for the channel regions and the protective material may be deposited in amorphous form and are subsequently crystallized in an anneal step. The protective material may be silicon boron, silicon carbon or silicon germanium. The protective material induces greater grain boundaries in the crystallized silicon in the channel regions, thereby providing greater charge carrier mobility, greater conductivity and greater current densities.

公开(公告)号：US10741584B2

公开(公告)日：2020-08-11

申请号：US16809389

申请日：2020-03-04

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari ,  Wu-Yi Henry Chien ,  Scott Brad Herner

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/768 ,  H01L21/28

Abstract: A method to ease the fabrication of high aspect ratio three dimensional memory structures for memory cells with feature sizes of 20 nm or less, or with a high number of memory layers. The present invention also provides an improved isolation between adjacent memory cells along the same or opposite sides of an active strip. The improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells along the same side of an active strip, and by staggering memory cells of opposite sides of the active strip.

公开(公告)号：US10741581B2

公开(公告)日：2020-08-11

申请号：US16510610

申请日：2019-07-12

Applicant: Sunrise Memory Corporation

Inventor： Eli Harari ,  Scott Brad Herner ,  Wu-Yi Henry Chien

IPC: H01L21/00 ,  H01L27/11582 ,  H01L21/306 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L29/08 ,  H01L21/027 ,  H01L21/3105 ,  H01L27/00

Abstract: A process for manufacturing a 3-dimensional memory structure includes: (a) providing one or more active layers over a planar surface of a semiconductor substrate, each active layer comprising (i) first and second semiconductor layers of a first conductivity; (ii) a dielectric layer separating the first and second semiconductor layer; and (ii) one or more sacrificial layers, at least one of sacrificial layers being adjacent the first semiconductor layer; (b) etching the active layers to create a plurality of active stacks and a first set of trenches each separating and exposing sidewalls of adjacent active stacks; (c) filling the first set of trenches by a silicon oxide; (d) patterning and etching the silicon oxide to create silicon oxide columns each abutting adjacent active stacks and to expose portions of one or more sidewalls of the active stacks; (e) removing the sacrificial layers from exposed portions of the sidewalls by isotropic etching through the exposed portions of the sidewalls of the active stacks to create corresponding cavities in the active layers; (f) filling the cavities in the active stacks by a metallic or conductor material; (g) recessing the dielectric layer from the exposed sidewalls of the active stacks; and (h) filling recesses in the dielectric layer by a third semiconductor layer of a second conductivity opposite the first conductivity.

公开(公告)号：US20200098779A1

公开(公告)日：2020-03-26

申请号：US16577469

申请日：2019-09-20

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Raul Adrian Cernea ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H01L27/11578 ,  H01L27/11568 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/285 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/768

Abstract: Various methods and various staircase structures formed out of the active strips of a memory structure (e.g., a memory array having a three-dimensional arrangement of NOR memory strings) above a semiconductor substrate allows efficient electrical connections to semiconductor layers within the active strips.

公开(公告)号：US12096630B2

公开(公告)日：2024-09-17

申请号：US16577469

申请日：2019-09-20

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Raul Adrian Cernea ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H10B43/20 ,  H01L21/285 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B43/30

CPC classification number: H10B43/20 ,  H01L21/28525 ,  H01L21/30604 ,  H01L21/32133 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53271 ,  H10B43/30

Abstract: Various methods and various staircase structures formed out of the active strips of a memory structure (e.g., a memory array having a three-dimensional arrangement of NOR memory strings) above a semiconductor substrate allows efficient electrical connections to semiconductor layers within the active strips.

公开(公告)号：US20240179919A1

公开(公告)日：2024-05-30

申请号：US18436365

申请日：2024-02-08

Applicant: SunRise Memory Corporation

Inventor： Tianhong Yan ,  Scott Brad Herner ,  Jie Zhou ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H10B43/40 ,  H01L21/02 ,  H01L21/225 ,  H01L21/311 ,  H01L21/3205 ,  H01L23/528 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/40 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/2251 ,  H01L21/31111 ,  H01L21/32053 ,  H01L23/528 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66742 ,  H01L29/78642 ,  H10B43/10 ,  H10B43/27

Abstract: A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

公开(公告)号：US11844204B2

公开(公告)日：2023-12-12

申请号：US18050937

申请日：2022-10-28

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Vinod Purayath ,  Jie Zhou ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H01L29/66 ,  H10B99/00 ,  H01L29/786 ,  H01L21/3065

CPC classification number: H10B99/00 ,  H01L21/3065 ,  H01L29/6675 ,  H01L29/78642 ,  H01L29/78663 ,  H01L29/78672

Abstract: A process includes (a) providing a semiconductor substrate having a planar surface; (b) forming a plurality of thin-film layers above the planar surface of the semiconductor substrate, one on top of another, including among the thin-film layers first and second isolation layers, wherein a significantly greater concentration of a first dopant specie is provided in the first isolation layer than in the second isolation layer; (c) etching along a direction substantially orthogonal to the planar surface through the thin-films to create a trench having sidewalls that expose the thin-film layers; (d) depositing conformally a semiconductor material on the sidewalls of the trench; (e) annealing the first isolation layer at a predetermined temperature and a predetermined duration such that the first isolation layer act as a source of the first dopant specie which dopes a portion of the semiconductor material adjacent the first isolation layer; and (f) selectively etching the semiconductor material to remove the doped portion of the semiconductor material without removing the remainder of the semiconductor material.

公开(公告)号：US20230157019A1

公开(公告)日：2023-05-18

申请号：US17527972

申请日：2021-11-16

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Vinod Purayath ,  Wu-Yi Henry Chien

IPC: H01L27/11578 ,  H01L27/11551

CPC classification number: H01L27/11578 ,  H01L27/11551

Abstract: In the highly efficient fabrication processes for HNOR arrays provided herein, the channel regions of the storage transistors in the HNOR arrays are protected by a protective layer after deposition until the subsequent deposition of a charge-trapping material before forming local word lines. Both the silicon for the channel regions and the protective material may be deposited in amorphous form and are subsequently crystallized in an anneal step. The protective material may be silicon boron, silicon carbon or silicon germanium. The protective material induces greater grain boundaries in the crystallized silicon in the channel regions, thereby providing greater charge carrier mobility, greater conductivity and greater current densities.