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    DRAM WITH DUAL LEVEL WORD LINES
    11.
    发明申请
    DRAM WITH DUAL LEVEL WORD LINES 有权

    公开(公告)号：US20140021523A1

    公开(公告)日：2014-01-23

    申请号：US13551766

    申请日：2012-07-18

    申请人： Babar A. Khan ,  Effendi Leobandung

    发明人： Babar A. Khan ,  Effendi Leobandung

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/10867 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10891 ,  H01L27/1203 ,  H01L29/945

    摘要： A top semiconductor layer and conductive cap structures over deep trench capacitors are simultaneously patterned by an etch. Each patterned portion of the conductive cap structures constitutes a conductive cap structure, which laterally contacts a semiconductor material portion that is one of patterned remaining portions of the top semiconductor layer. Gate electrodes are formed as discrete structures that are not interconnected. After formation and planarization of a contact-level dielectric layer, passing gate lines are formed above the contact-level dielectric layer in a line level to provide electrical connections to the gate electrodes. Gate electrodes and passing gate lines that are electrically connected among one another constitute a gate line that is present across two levels.

    STRUCTURE AND METHOD FOR MANUFACTURING TRENCH CAPACITANCE
    14.
    发明申请
    STRUCTURE AND METHOD FOR MANUFACTURING TRENCH CAPACITANCE 有权
    用于制造TRENCH电容的结构和方法

    公开(公告)号：US20100038751A1

    公开(公告)日：2010-02-18

    申请号：US12191430

    申请日：2008-08-14

    申请人： HUILONG ZHU ,  Babar A. Khan ,  Xi Li ,  Joyce C. Liu ,  Thomas A. Wallner

    发明人： HUILONG ZHU ,  Babar A. Khan ,  Xi Li ,  Joyce C. Liu ,  Thomas A. Wallner

    IPC分类号： H01L29/00 ,  H01L21/20

    CPC分类号： H01L29/66181 ,  H01L27/10861

    摘要： A deep trench (DT) capacitor comprises a trench in a silicon layer, a buried plate surrounding the trench, a dielectric layer lining the trench, and a node conductor in the trench. The top surface of the poly node is higher than the surface of the silicon layer, so that it is high enough to ensure that a nitride liner used as a CMP etch stop for STI oxide surrounding a top portion of the poly node will be higher than the STI oxide, so that the nitride liner can be removed prior to forming a silicide contact on top of the poly node.

    摘要翻译： 深沟槽（DT）电容器包括硅层中的沟槽，围绕沟槽的掩埋板，衬套沟槽的电介质层和沟槽中的节点导体。 多晶硅节点的顶表面高于硅层的表面，使得其足够高以确保用作CMP蚀刻的氮化物衬垫停止用于围绕多晶硅节点的顶部的STI氧化物将高于 STI氧化物，使得氮化物衬垫可以在在多晶硅节点的顶部形成硅化物接触之前被去除。

    Secure and dense SRAM cells in EDRAM technology
    15.
    发明授权
    Secure and dense SRAM cells in EDRAM technology 失效
    EDRAM技术中的安全且密集的SRAM单元

    公开(公告)号：US06507511B1

    公开(公告)日：2003-01-14

    申请号：US09969360

    申请日：2001-10-02

    申请人： John E. Barth, Jr. ,  Subramanian S. Iyer ,  Babar A. Khan ,  Robert C. Wong

    发明人： John E. Barth, Jr. ,  Subramanian S. Iyer ,  Babar A. Khan ,  Robert C. Wong

    IPC分类号： G11C1124

    CPC分类号： G11C11/4125

    摘要： Addition of capacitance to the storage nodes of static random access memory cells and other types of integrated circuits substantially increases Qcrit and substantially eliminates soft errors due to alpha particles; susceptibility to which would otherwise increase as integrated circuits are scaled to smaller sizes and manufactured at increased integration densities. Formation of the added capacitance as deep trench capacitors avoids any constraint on circuit or memory cell layout. Degradation of performance is avoided and performance potentially improved by permitting alteration of proportions of pull-down and pass gate transistors in view of the increased stability imparted by the added capacitors. One of the capacitor electrodes is preferably shorted to the supply voltage through an impurity well. Thus, the memory cell size can be reduced while greatly reducing susceptibility to soft errors; contrary to the effects of scaling at current and foreseeable feature size regimes.

    摘要翻译： 向静态随机存取存储器单元和其他类型的集成电路的存储节点增加电容大大增加了Qcrit并且基本消除了由于α粒子引起的软错误; 随着集成电路被缩放到更小的尺寸并且以增加的集成密度制造，易受性将随之增加。 形成作为深沟槽电容器的附加电容避免了对电路或存储器单元布局的任何限制。 鉴于增加的电容器增加的稳定性，可以通过允许下拉和栅极晶体管的比例的改变来避免性能的降低和性能的提高。 电容器电极之一优选通过杂质井短路到电源电压。 因此，可以减小存储单元尺寸，同时大大降低对软错误的敏感性; 与当前和可预见的特征尺寸体系的缩放效应相反。

    DRAM with dual level word lines
    19.
    发明授权
    DRAM with dual level word lines 有权
    DRAM具有双电平字线

    公开(公告)号：US08779490B2

    公开(公告)日：2014-07-15

    申请号：US13551766

    申请日：2012-07-18

    申请人： Babar A. Khan ,  Effendi Leobandung

    发明人： Babar A. Khan ,  Effendi Leobandung

    IPC分类号： H01L27/108 ,  H01L29/94 ,  H01L29/66 ,  H01L21/8242 ,  H01L21/336 ,  H01L21/8234

    CPC分类号： H01L27/10867 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10891 ,  H01L27/1203 ,  H01L29/945

    摘要： A top semiconductor layer and conductive cap structures over deep trench capacitors are simultaneously patterned by an etch. Each patterned portion of the conductive cap structures constitutes a conductive cap structure, which laterally contacts a semiconductor material portion that is one of patterned remaining portions of the top semiconductor layer. Gate electrodes are formed as discrete structures that are not interconnected. After formation and planarization of a contact-level dielectric layer, passing gate lines are formed above the contact-level dielectric layer in a line level to provide electrical connections to the gate electrodes. Gate electrodes and passing gate lines that are electrically connected among one another constitute a gate line that is present across two levels.

    摘要翻译： 深沟槽电容器上的顶部半导体层和导电帽结构通过蚀刻同时构图。 导电盖结构的每个图案化部分构成导电盖结构，其横向接触作为顶部半导体层的图案化剩余部分之一的半导体材料部分。 栅电极形成为不互连的离散结构。 在接触电介质层的形成和平坦化之后，通过栅极线形成在接触电介质层上方的线路电平以提供与栅电极的电连接。 彼此电连接的栅极电极和通过栅极线构成跨越两个电平存在的栅极线。