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公开(公告)号：US10714485B2
公开(公告)日：2020-07-14
申请号：US16126875
申请日：2018-09-10
发明人： Chih-Liang Chen , Chih-Ming Lai , Charles Chew-Yuen Young , Chin-Yuan Tseng , Jiann-Tyng Tzeng , Kam-Tou Sio , Ru-Gun Liu , Wei-Liang Lin , L. C. Chou
IPC分类号： H01L27/11 , H01L21/8234 , H01L27/088 , H01L21/308 , H01L29/78 , H01L29/66 , H01L21/311
摘要： A semiconductor device including multiple fins. At least a first set of fins among the multiple fins is substantially parallel. At least a second set of fins among the multiple fins is substantially collinear. For any given first and second fins of the multiple fins having corresponding first and second fin-thicknesses, the second fin-thickness is less than plus or minus about 50% of the first fin-thickness.
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公开(公告)号：US09442510B2
公开(公告)日：2016-09-13
申请号：US14613817
申请日：2015-02-04
摘要： A clock gating circuit includes a first transistor, a first inverter and a second transistor. A first terminal of the first transistor receives a clock input signal. A second terminal of the first transistor is coupled to a first node. The first transistor adjusts a voltage of the first node to a first voltage based on the clock input signal. The first inverter is coupled to the first node and receives the voltage of the first node, and outputs a clock output signal. A first terminal of the second transistor receives the clock input signal. A second terminal of the second transistor is coupled to the first node and a second node. The second transistor adjusts the voltage of the first node or the second node to the second voltage, based on the clock input signal.
摘要翻译： 时钟选通电路包括第一晶体管，第一反相器和第二晶体管。 第一晶体管的第一端接收时钟输入信号。 第一晶体管的第二端子耦合到第一节点。 第一晶体管基于时钟输入信号将第一节点的电压调整到第一电压。 第一反相器耦合到第一节点并接收第一节点的电压，并输出时钟输出信号。 第二晶体管的第一端子接收时钟输入信号。 第二晶体管的第二端子耦合到第一节点和第二节点。 第二晶体管基于时钟输入信号将第一节点或第二节点的电压调整到第二电压。
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公开(公告)号：US11100273B2
公开(公告)日：2021-08-24
申请号：US16674869
申请日：2019-11-05
发明人： Shih-Wei Peng , Chih-Liang Chen , Charles Chew-Yuen Young , Hui-Zhong Zhuang , Jiann-Tyng Tzeng , Shun Li Chen , Wei-Cheng Lin
IPC分类号： G06F30/00 , G06F30/398 , H01L27/02 , H01L27/118 , G06F30/39 , G06F30/394
摘要： A method of forming an integrated circuit includes generating, by a processor, a layout design of the integrated circuit based on a set of design rules and manufacturing the integrated circuit based on the layout design. The generating of the layout design includes generating a set of active region layout patterns extending in a first direction, generating a set of gate layout patterns extending in a second direction, and generating a cut feature layout pattern extending in the first direction, overlapping at least a first gate layout pattern of the set of gate layout patterns, being separated from the set of active region layout patterns in the second direction by at least a first distance. The first distance satisfying a first design rule of the set of design rules.
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公开(公告)号：US10366200B2
公开(公告)日：2019-07-30
申请号：US15258932
申请日：2016-09-07
发明人： Wei-Cheng Lin , Chih-Liang Chen , Chih-Ming Lai , Charles Chew-Yuen Young , Jiann-Tyng Tzeng , Kam-Tou Sio , Ru-Gun Liu , Shih-Wei Peng , Wei-Chen Chien
IPC分类号： G06F17/50
摘要： A method of forming a layout design for fabricating an integrated circuit is disclosed. The method includes generating a first layout of the integrated circuit based on design criteria, generating a standard cell layout of the integrated circuit, generating a via color layout of the integrated circuit based on the first layout and the standard cell layout and performing a color check on the via color layout based on design rules. The first layout having a first set of vias arranged in first rows and first columns. The standard cell layout having standard cells and a second set of vias arranged in the standard cells. The via color layout having a third set of vias. The third set of vias including a portion of the second set of vias and corresponding locations, and color of corresponding sub-set of vias.
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公开(公告)号：US09917050B2
公开(公告)日：2018-03-13
申请号：US15331363
申请日：2016-10-21
发明人： Chih-Liang Chen , Chih-Ming Lai , Kam-Tou Sio , Ru-Gun Liu , Meng-Hung Shen , Chun-Hung Liou , Shu-Hui Sung , Charles Chew-Yuen Young
IPC分类号： G01R31/26 , H01L23/522 , H01L21/768 , H01L23/535 , H01L23/48 , H01L21/8234 , H01L23/528 , H01L23/532 , H01L27/088 , H01L29/40 , H01L29/423 , H01L29/45 , H01L29/66
CPC分类号： H01L23/5226 , H01L21/768 , H01L21/76819 , H01L21/76829 , H01L21/76879 , H01L21/76895 , H01L21/76897 , H01L21/823418 , H01L21/823437 , H01L21/823475 , H01L23/48 , H01L23/5283 , H01L23/5329 , H01L23/535 , H01L27/088 , H01L29/401 , H01L29/42364 , H01L29/456 , H01L29/665 , H01L29/66583 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate having source and drain regions, and a channel region arranged between the source and drain regions. The device further includes a gate structure over the substrate and adjacent to the channel region. The gate structure includes a gate stack, a spacer on sidewalls of the gate stack, and a conductor over the gate stack. The device further includes a first contact feature over the substrate and electrically connecting to at least one of the source and drain regions. A top surface of the first contact feature is lower than a top surface of the gate structure. The device further includes a first dielectric layer over the first contact feature. A top surface of the first dielectric layer is below or substantially co-planar with the top surface of the gate structure. The conductor at most partially overlaps in plan view with the first dielectric layer.
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公开(公告)号：US09741654B2
公开(公告)日：2017-08-22
申请号：US15332605
申请日：2016-10-24
IPC分类号： H01L23/52 , H01L29/40 , H01L21/4763 , H01L21/44 , H01L23/522 , H01L21/768 , H01L23/485 , H01L23/528 , H01L23/532
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76879 , H01L21/76895 , H01L23/485 , H01L23/5222 , H01L23/528 , H01L23/53209 , H01L23/5328 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a first conductive line on a first metal level of the integrated circuit. The integrated circuit further includes a second conductive line on a second metal level of the integrated circuit. The integrated circuit further includes a slot via electrically connecting the first conductive line with the second conductive line. The slot via overlaps with the first conductive line and the second conductive line. The slot via extends beyond a periphery of at least one of the first conductive line or the second conductive line.
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公开(公告)号：US20170040259A1
公开(公告)日：2017-02-09
申请号：US15331363
申请日：2016-10-21
发明人： Chih-Liang Chen , Chih-Ming Lai , Kam-Tou Sio , Ru-Gun Liu , Meng-Hung Shen , Chun-Hung Liou , Shu-Hui Sung , Charles Chew-Yuen Young
IPC分类号： H01L23/522 , H01L29/423 , H01L29/45 , H01L21/8234 , H01L27/088 , H01L29/40 , H01L21/768 , H01L23/528 , H01L23/532
CPC分类号： H01L23/5226 , H01L21/768 , H01L21/76819 , H01L21/76829 , H01L21/76879 , H01L21/76895 , H01L21/76897 , H01L21/823418 , H01L21/823437 , H01L21/823475 , H01L23/48 , H01L23/5283 , H01L23/5329 , H01L23/535 , H01L27/088 , H01L29/401 , H01L29/42364 , H01L29/456 , H01L29/665 , H01L29/66583 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate having source and drain regions, and a channel region arranged between the source and drain regions. The device further includes a gate structure over the substrate and adjacent to the channel region. The gate structure includes a gate stack, a spacer on sidewalls of the gate stack, and a conductor over the gate stack. The device further includes a first contact feature over the substrate and electrically connecting to at least one of the source and drain regions. A top surface of the first contact feature is lower than a top surface of the gate structure. The device further includes a first dielectric layer over the first contact feature. A top surface of the first dielectric layer is below or substantially co-planar with the top surface of the gate structure. The conductor at most partially overlaps in plan view with the first dielectric layer.
摘要翻译： 半导体器件包括具有源区和漏区的衬底以及布置在源区和漏区之间的沟道区。 该器件还包括在衬底上并与沟道区相邻的栅极结构。 栅极结构包括栅极堆叠，栅极堆叠的侧壁上的间隔物和栅极堆叠上的导体。 该器件还包括在衬底上的第一接触特征，并且电连接到源区和漏区中的至少一个。 第一接触特征的顶表面低于栅极结构的顶表面。 该装置还包括在第一接触特征上的第一介电层。 第一电介质层的顶表面与栅极结构的顶表面低于或基本上共平面。 导体在与第一介电层的平面图中最多部分重叠。
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公开(公告)号：US09478492B2
公开(公告)日：2016-10-25
申请号：US14600695
申请日：2015-01-20
IPC分类号： H01L23/52 , H01L29/40 , H01L21/4763 , H01L21/44 , H01L23/522 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76879 , H01L21/76895 , H01L23/485 , H01L23/5222 , H01L23/528 , H01L23/53209 , H01L23/5328 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a first conductive line on a first metal level of the integrated circuit. The integrated circuit further includes a second conductive line on a second metal level of the integrated circuit. The integrated circuit further includes a slot via electrically connecting the first conductive line with the second conductive line. The slot via overlaps with the first conductive line and the second conductive line. The slot via extends beyond a periphery of at least one of the first conductive line or the second conductive line.
摘要翻译： 集成电路包括集成电路的第一金属层上的第一导线。 集成电路还包括在集成电路的第二金属电平上的第二导线。 集成电路还包括通过电连接第一导线与第二导线的槽。 槽通道与第一导线和第二导线重叠。 狭槽通孔延伸超过第一导电线或第二导线中的至少一个的周边。
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公开(公告)号：US11842137B2
公开(公告)日：2023-12-12
申请号：US17406699
申请日：2021-08-19
发明人： Shih-Wei Peng , Chih-Liang Chen , Charles Chew-Yuen Young , Hui-Zhong Zhuang , Jiann-Tyng Tzeng , Shun Li Chen , Wei-Cheng Lin
IPC分类号： G06F30/00 , G06F30/398 , H01L27/02 , H01L27/118 , G06F30/39 , G06F30/394
CPC分类号： G06F30/398 , G06F30/39 , G06F30/394 , H01L27/0207 , H01L27/11807 , H01L2027/11875
摘要： An integrated circuit includes a set of gates, a first, second and third conductive structure, and a first, second and third via. The set of gates includes a first, second and third gate. The first, second and third conductive structure extend in the first direction and are located on a second level. The first via couples the first conductive structure and the first gate. The second via couples the second conductive structure and the second gate. The third via couples the third conductive structure and the third gate. The first, second and third via are in a right angle configuration. The first and second gate are separated from each other by a first pitch. The first and third gate are separated from each other by a removed gate portion. The first and second conductive structure are separated from each other in the first direction.
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20.发明公开公开(公告)号：US20230368829A1
公开(公告)日：2023-11-16
申请号：US18355510
申请日：2023-07-20
发明人： Jack Liu , Charles Chew-Yuen Young
CPC分类号： G11C11/1673 , G11C11/1693 , H01F10/3254 , G11C11/161 , G11C11/15 , G11C11/02 , H10B61/22 , H10N50/80
摘要： Some embodiments of the present disclosure relate to a memory device. The memory device includes an active current path including a data storage element; and a reference current path including a reference resistance element. The reference resistance element has a resistance that differs from a resistance of the data storage element. A delay-sensing element has a first input coupled to the active current path and a second input coupled to the reference current path. The delay-sensing element is configured to sense a timing delay between a first signal on the active current path and a second signal on the reference current path. The delay-sensing element is further configured to determine a data state stored in the data storage element based on the timing delay.
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