公开(公告)号：US08932951B2

公开(公告)日：2015-01-13

申请号：US14046255

申请日：2013-10-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Yuan Wu ,  Kong-Beng Thei ,  Chiung-Han Yeh ,  Harry-Hak-Lay Chuang ,  Mong-Song Liang

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L21/762

CPC分类号： H01L21/76883 ,  H01L21/76229

摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.

公开(公告)号：US20190035914A1

公开(公告)日：2019-01-31

申请号：US16134103

申请日：2018-09-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Harry-Hak-Lay Chuang ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Chiung-Han Yeh ,  Lee-Wee Teo ,  Yu-Ying Hsu ,  Bao-Ru Young

IPC分类号： H01L29/66 ,  H01L49/02 ,  H01L27/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/08

CPC分类号： H01L29/66545 ,  H01L21/823842 ,  H01L27/0629 ,  H01L27/0802 ,  H01L27/0922 ,  H01L28/20 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2223/6672

摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

公开(公告)号：US10084061B2

公开(公告)日：2018-09-25

申请号：US15925323

申请日：2018-03-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Harry-Hak-Lay Chuang ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Chiung-Han Yeh ,  Lee-Wee Teo ,  Yu-Ying Hsu ,  Bao-Ru Young

IPC分类号： H01L27/01 ,  H01L29/66 ,  H01L29/78 ,  H01L49/02 ,  H01L27/092 ,  H01L27/06 ,  H01L21/8238 ,  H01L27/08

CPC分类号： H01L29/66545 ,  H01L21/823842 ,  H01L27/0629 ,  H01L27/0802 ,  H01L27/0922 ,  H01L28/20 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2223/6672

摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

公开(公告)号：US20180211901A1

公开(公告)日：2018-07-26

申请号：US15924997

申请日：2018-03-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jui-Pin Hung ,  Jing-Cheng Lin ,  Po-Hao Tsai ,  Yi-Jou Lin ,  Shuo-Mao Chen ,  Chiung-Han Yeh ,  Der-Chyang Yeh

IPC分类号： H01L23/48 ,  H01L21/56 ,  H01L21/48

CPC分类号： H01L23/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76843 ,  H01L21/82 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/528 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/82

摘要： An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.

公开(公告)号：US09679988B2

公开(公告)日：2017-06-13

申请号：US14543169

申请日：2014-11-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Harry-Hak-Lay Chuang ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Chiung-Han Yeh ,  Lee-Wee Teo ,  Yu-Ying Hsu ,  Bao-Ru Young

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L49/02

CPC分类号： H01L29/66545 ,  H01L21/823842 ,  H01L27/0629 ,  H01L27/0802 ,  H01L27/0922 ,  H01L28/20 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2223/6672

摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

公开(公告)号：US09040381B2

公开(公告)日：2015-05-26

申请号：US14080014

申请日：2013-11-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Shang-Yun Hou ,  Der-Chyang Yeh ,  Shuo-Mao Chen ,  Chiung-Han Yeh ,  Yi-Jou Lin

IPC分类号： H01L21/20 ,  H01L21/56 ,  H01L23/64 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L27/01 ,  H01L49/02

CPC分类号： H01L21/56 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/5389 ,  H01L23/64 ,  H01L24/19 ,  H01L27/016 ,  H01L28/00 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19011 ,  H01L2924/1903 ,  H01L2924/19031 ,  H01L2924/19033 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2924/00

摘要： A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A Post-Passivation Interconnect (PPI) line is disposed over the passivation layer and electrically coupled to the metal pad. An Under-Bump Metallurgy (UBM) is disposed over and electrically coupled to the PPI line. A passive device includes a portion at a same level as the UBM. The portion of the passive device is formed of a same material as the UBM.

摘要翻译： 一种器件包括衬底，衬底上的金属焊盘以及具有在金属焊盘上的部分的钝化层。 后钝化互连（PPI）线设置在钝化层上并电耦合到金属焊盘。 爆炸性冶金（UBM）被布置在电气耦合到PPI线路上。 无源设备包括与UBM处于相同水平的部分。 无源器件的部分由与UBM相同的材料形成。

公开(公告)号：US08669153B2

公开(公告)日：2014-03-11

申请号：US13794621

申请日：2013-03-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chiung-Han Yeh ,  Ming-Yuan Wu ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

IPC分类号： H01L21/8238

CPC分类号： H01L29/66606 ,  H01L21/823814 ,  H01L21/823871

摘要： A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact.

摘要翻译： 提供了一种提供基板的方法， 在衬底中形成晶体管，晶体管具有虚拟栅极; 在衬底和晶体管上形成介电层; 在介电层中形成接触特征; 并且在形成接触特征之后，用金属栅极替换晶体管的虚拟栅极。 示例性接触特征是双重接触。

公开(公告)号：US11018241B2

公开(公告)日：2021-05-25

申请号：US16876571

申请日：2020-05-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Harry-Hak-Lay Chuang ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Chiung-Han Yeh ,  Lee-Wee Teo ,  Yu-Ying Hsu ,  Bao-Ru Young

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L27/06 ,  H01L27/092 ,  H01L49/02 ,  H01L21/8238 ,  H01L23/62 ,  H01L27/08

摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

公开(公告)号：US20200279935A1

公开(公告)日：2020-09-03

申请号：US16876571

申请日：2020-05-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Harry-Hak-Lay Chuang ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Chiung-Han Yeh ,  Lee-Wee Teo ,  Yu-Ying Hsu ,  Bao-Ru Young

IPC分类号： H01L29/66 ,  H01L27/06 ,  H01L27/092 ,  H01L49/02 ,  H01L29/78 ,  H01L21/8238

摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

公开(公告)号：US09455344B2

公开(公告)日：2016-09-27

申请号：US14284559

申请日：2014-05-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Harry-Hak-Lay Chuang ,  Kong-Beng Thei ,  Chiung-Han Yeh ,  Ming-Yuan Wu ,  Mong-Song Liang

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L29/78 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/7833

摘要： A device having a gate where the profile of the gate provides a first width at a top region and a second width at a bottom region is described. The gate may include tapered sidewalls. The gate may be a metal gate structure.

摘要翻译： 描述了具有栅极的器件，其中栅极的轮廓在顶部区域提供第一宽度并且在底部区域提供第二宽度。 栅极可以包括锥形侧壁。 栅极可以是金属栅极结构。