-
11.
公开(公告)号:US09666553B2
公开(公告)日:2017-05-30
申请号:US14740190
申请日:2015-06-15
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Rajen Manicon Murugan , Minhong Mi , Gary Paul Morrison , Jie Chen , Kenneth Robert Rhyner , Stanley Craig Beddingfield , Chittranjan Mohan Gupta , Django Earl Trombley
CPC classification number: H01L23/66 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2223/6627 , H01L2223/6655 , H01L2223/6677 , H01L2223/6683 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2924/00014 , H01L2924/1423 , H01L2924/15173 , H01L2924/15311 , H01L2924/30111 , H01Q1/2283 , H01Q1/3233 , H01Q23/00 , H05K1/0222 , H05K1/0243 , H05K1/0245 , H05K1/0251 , H05K1/181 , H05K2201/09609 , H05K2201/10734 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/05599 , H01L2224/85399
Abstract: A millimeter wave integrated circuit (IC) chip. The IC chip comprises an IC die and a wire bond ball grid array package encapsulating the IC die. The wire bond ball grid array package comprises a solder ball array, a millimeter wave transmit channel, and a millimeter wave receive channel, wherein each millimeter wave transmit and receive channel electrically couples the IC die to a signal ball of the solder ball array and is configured to resonate at an operating frequency band of the millimeter wave IC chip.
-
公开(公告)号:US12243911B2
公开(公告)日:2025-03-04
申请号:US17017642
申请日:2020-09-10
Applicant: Texas Instruments Incorporated
Inventor: Matthew David Romig , Enis Tuncer , Rajen Manicon Murugan , Yiqi Tang
IPC: H01L29/06 , H01L21/48 , H01L21/56 , H01L23/31 , H01L23/498
Abstract: In described examples of an isolation device, an isolation die that has a set of bond pads is mounted on a first lead frame that has a set of leads. A portion of the bond pads are coupled to respective leads. A first mold material encapsulates the isolation device and the first lead frame forming a first package. The first package is mounted on a second lead frame that has a set of leads. A portion of the first lead frame leads is coupled to respective ones of the second lead frame leads. A second mold material encapsulates the first package and the second lead frame.
-
公开(公告)号:US12243849B2
公开(公告)日:2025-03-04
申请号:US17491378
申请日:2021-09-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Chittranjan Mohan Gupta , Yiqi Tang , Rajen Manicon Murugan , Jie Chen , Tianyi Luo
IPC: H01L25/065 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/498 , H01L25/00
Abstract: In examples, a semiconductor package comprises a substrate and multiple columns of semiconductor dies positioned approximately in parallel along a length of the substrate. The package also includes multiple passive components positioned between the multiple columns of semiconductor dies, the multiple passive components angled between 30 and 60 degrees relative to the length of the substrate, a pair of the multiple passive components having a gap therebetween that is configured to permit mold compound flow through capillary action. The package also includes a mold compound covering the substrate, the multiple columns of semiconductor dies, and the multiple passive components.
-
公开(公告)号:US12224480B2
公开(公告)日:2025-02-11
申请号:US17736653
申请日:2022-05-04
Applicant: Texas Instruments Incorporated
Inventor: Yiqi Tang , Rajen Manicon Murugan
Abstract: An example semiconductor package comprises a patch antenna formed in a first conductor layer of a multilayer package substrate. The multilayer package substrate comprises conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers. The multilayer package substrate has a board side surface opposite a device side surface. The semiconductor package further comprises a semiconductor die mounted to the device side surface of the multilayer package substrate spaced from and coupled to the patch antenna. An antenna horn is mounted to the device side surface and aligned with the patch antenna using a mounting structure. The semiconductor package further comprises a reflector formed on a second conductor layer in the multilayer package substrate. The second conductor layer is positioned closer to the board side surface of the multilayer package substrate compared to the patch antenna.
-
公开(公告)号:US11978709B2
公开(公告)日:2024-05-07
申请号:US17752037
申请日:2022-05-24
Applicant: Texas Instruments Incorporated
Inventor: Vivek Swaminathan Sridharan , Yiqi Tang , Christopher Daniel Manack , Rajen Manicon Murugan , Liang Wan , Hiep Xuan Nguyen
IPC: H01L23/60 , H01L23/00 , H01L23/495 , H01L33/00 , H01L33/62 , H01L21/683 , H01L25/16
CPC classification number: H01L23/60 , H01L23/49503 , H01L23/4952 , H01L23/49575 , H01L24/28 , H01L24/82 , H01L33/005 , H01L33/62 , H01L21/6835 , H01L24/24 , H01L24/25 , H01L25/167 , H01L2933/005 , H01L2933/0066
Abstract: A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.
-
公开(公告)号:US11881460B2
公开(公告)日:2024-01-23
申请号:US18172208
申请日:2023-02-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Yiqi Tang , Li Jiang , Rajen Manicon Murugan
IPC: H01L23/00 , H01L23/552 , H01L23/58 , H01L21/50 , H01L21/52
CPC classification number: H01L23/585 , H01L21/50 , H01L21/52 , H01L23/552 , H01L23/562 , H01L23/564
Abstract: In examples, a semiconductor package comprises a ceramic substrate and first and second metal layers covered by the ceramic substrate. The first metal layer is configured to carry signals at least in a 20 GHz to 28 GHz frequency range. The package comprises a semiconductor die positioned above the first and second metal layers and coupled to the first metal layer. The package comprises a ground shield positioned in a horizontal plane between the semiconductor die and the first metal layer, the ground shield including an orifice above a portion of the first metal layer. The package includes a metal seal ring coupled to a top surface of the ceramic substrate, the metal seal ring having a segment that is vertically aligned with a segment of the ground shield. The segment of the ground shield is between the orifice of the ground shield and a horizontal center of the ground shield. The package comprises a metal lid coupled to a top surface of the metal seal ring.
-
公开(公告)号:US20230207430A1
公开(公告)日:2023-06-29
申请号:US18177273
申请日:2023-03-02
Applicant: Texas Instruments Incorporated
Inventor: Rajen Manicon Murugan , Yiqi Tang
IPC: H01L23/495 , H01L21/56 , H01L21/48 , H01L23/00 , H01L23/31
CPC classification number: H01L23/49534 , H01L23/49589 , H01L23/49558 , H01L23/49575 , H01L21/565 , H01L21/563 , H01L21/4821 , H01L24/16 , H01L23/3107 , H01L2224/16245
Abstract: A semiconductor package includes a multilayer package substrate with a top layer including top filled vias through a top dielectric layer and top metal layer providing a top surface for leads and traces connected to the leads, and a bottom layer including bottom filled vias including contact pads through a bottom dielectric and metal layer. The top filled vias are for connecting the bottom and top metal layer. The bottom metal filled vias are for connecting the bottom metal layer to the contact pads. An integrated circuit (IC) die has nodes in its circuitry connected to the bond pads. The IC die is flipchip mounted onto the leads. A passive device(s) is surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the leads. A mold compound is for encapsulating at least the IC die and passive device.
-
公开(公告)号:US20220209391A1
公开(公告)日:2022-06-30
申请号:US17138557
申请日:2020-12-30
Applicant: Texas Instruments Incorporated
Inventor: Yiqi Tang , Makarand Ramkrishna Kulkarni , Liang Wan , Rajen Manicon Murugan
IPC: H01Q1/22 , H01Q9/04 , H01L23/367 , H01L23/31 , H01L23/538 , H01L23/66 , H01L23/00 , H01L21/48 , H01L21/56 , H01L21/683 , H01P3/08
Abstract: An antenna in package (AIP) 400 includes an IC die 120 including bond pads 121 and a package substrate including the IC die mounted up and being completely embedded therein. The package substrate includes a top layer 418 including a top dielectric layer 418b, a top metal layer 418a including an antenna 418a1, and a bottom layer 415 including a bottom dielectric 415b and a bottom metal layer 415a including contact pads including a first contact pad 415a1, and filled vias 415c, 417c. The bond pads are electrically coupled by a connection including a filled via(s) for connecting to the top metal layer and/or the bottom metal layer. Metal pillars including a first metal pillar 132a are electrically are coupled to the first contact pad, and at least one filled via is electrically coupled to the first metal pillar for providing a transmission line from the first contact pad to the antenna.
-
公开(公告)号:US20220028770A1
公开(公告)日:2022-01-27
申请号:US17227722
申请日:2021-04-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Rajen Manicon Murugan , Yiqi Tang
IPC: H01L23/498 , H01L21/48 , H02M1/00
Abstract: A semiconductor device includes a die with a power converter module. The power converter module includes an output port and a return port. The semiconductor device also includes a connection assembly that includes pads configured to be coupled to circuit components of a printed circuit board (PCB). The connection assembly also includes a first layer patterned to include a first trace that is coupled to one of the output port and the return port and a second trace that is coupled to the other of the output port and return port. A second layer of the connection assembly is patterned to provide a first via between the first trace and a third layer and a second via between the first trace and the third layer. The third layer is patterned to provide a portion of a first conductive path and a portion of a second conductive path.
-
公开(公告)号:US20220028593A1
公开(公告)日:2022-01-27
申请号:US17383878
申请日:2021-07-23
Applicant: Texas Instruments Incorporated
Inventor: Yiqi Tang , Rajen Manicon Murugan , Jonathan Almeria Noquil
IPC: H01F17/00 , H01L23/495 , H05K1/16 , H01L23/522 , H01F27/28 , H01L23/498 , H01L21/56 , H01F41/04
Abstract: An electronic device includes a multilevel package substrate, conductive leads, a die, and a package structure. The multilevel package substrate has a first level, a second level, and a third level, each having patterned conductive features and molded dielectric features. The first level includes a first patterned conductive feature with multiple turns that form a first winding. The second level includes a second patterned conductive feature, and the third level includes a third patterned conductive feature with multiple turns that form a second winding. A first terminal of the die is coupled to the first end of the first winding, a second terminal of the die is coupled to the second end of the first winding, and a third terminal of the die is coupled to a first conductive lead. The package structure encloses the first die, the second die, and a portion of the multilevel package substrate.
-
-
-
-
-
-
-
-
-