公开(公告)号：US20170141101A1

公开(公告)日：2017-05-18

申请号：US15368958

申请日：2016-12-05

Applicant: Texas Instruments Incorporated

Inventor： Weidong Tian ,  YuGuo Wang ,  Tathagata Chatterjee ,  Rajni J. Aggarwal

IPC: H01L27/06 ,  H01L29/06 ,  H01L21/8249 ,  H01L29/45 ,  H01L29/417 ,  H01L29/739 ,  H01L29/10

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L27/092 ,  H01L29/0688 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/423 ,  H01L29/456 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7395

Abstract: An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base with a band barrier at least 25 meV high at a surface boundary of the intrinsic base, except at an emitter-base junction with an emitter, and except at a base-collector junction with a collector. The intrinsic base may be laterally surrounded by an extrinsic base with a higher dopant density than the intrinsic base, wherein a higher dopant density provides the band barrier at lateral surfaces of the intrinsic base. A gate may be disposed on a gate dielectric layer over a top surface boundary of the intrinsic base adjacent to the emitter. The gate is configured to accumulate the intrinsic base immediately under the gate dielectric layer, providing the band barrier at the top surface boundary of the intrinsic base.

公开(公告)号：US20170125479A1

公开(公告)日：2017-05-04

申请号：US14932949

申请日：2015-11-04

Applicant: Texas Instruments Incorporated

Inventor： Keith Ryan Green ,  Rajni J. Aggarwal ,  Ajit Sharma

IPC: H01L27/22 ,  H01L43/04 ,  H01L43/14 ,  H01L43/06

CPC classification number: H01L27/22 ,  H01L43/04 ,  H01L43/065 ,  H01L43/14

Abstract: A CMOS integrated circuit includes a Hall sensor having a Hall plate formed in a first isolation layer which is formed concurrently with a second isolation layer under a MOS transistor. A first shallow well with a conductivity type opposite from the first isolation layer is formed over, and extending to, the Hall plate. The first shallow well is formed concurrently with a second shallow well under the MOS transistor. The Hall sensor may be a horizontal Hall sensor for sensing magnetic fields oriented perpendicular to the top surface of the substrate of the integrated circuit, or may be a vertical Hall sensor for sensing magnetic fields oriented parallel to the top surface of the substrate of the integrated circuit.

公开(公告)号：US10339251B2

公开(公告)日：2019-07-02

申请号：US15495016

申请日：2017-04-24

Applicant: Texas Instruments Incorporated

Inventor： Ashesh Parikh ,  Chi-Chien Ho ,  Thomas John Smelko ,  Rajni J. Aggarwal

IPC: G06F17/50 ,  H01L21/66 ,  H01L21/8234

Abstract: A method to adjust transistor gate geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to form a reticle. A method to adjust transistor geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to compensate for transistor turn on voltage drop off where the transistor gate crosses the isolation/active interface.

公开(公告)号：US09548298B1

公开(公告)日：2017-01-17

申请号：US14942979

申请日：2015-11-16

Applicant: Texas Instruments Incorporated

Inventor： Weidong Tian ,  YuGuo Wang ,  Tathagata Chatterjee ,  Rajni J. Aggarwal

IPC: H01L21/338 ,  H01L27/06 ,  H01L29/732 ,  H01L21/8238 ,  H01L21/8222

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L27/092 ,  H01L29/0688 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/423 ,  H01L29/456 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7395

Abstract: An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base with a band barrier at least 25 meV high at a surface boundary of the intrinsic base, except at an emitter-base junction with an emitter, and except at a base-collector junction with a collector. The intrinsic base may be laterally surrounded by an extrinsic base with a higher dopant density than the intrinsic base, wherein a higher dopant density provides the band barrier at lateral surfaces of the intrinsic base. A gate may be disposed on a gate dielectric layer over a top surface boundary of the intrinsic base adjacent to the emitter. The gate is configured to accumulate the intrinsic base immediately under the gate dielectric layer, providing the band barrier at the top surface boundary of the intrinsic base.

Abstract translation: 集成电路包括NMOS晶体管，PMOS晶体管和垂直双极晶体管。 垂直双极晶体管具有在本征基极的表面边界处具有至少25meV高的带势垒的本征基极，除了在与发射极的发射极 - 基极结之外，并且除了在与集电极的基极 - 集电极结之外。 本征碱可以被具有比本征碱更高的掺杂剂密度的外在碱基侧向包围，其中较高的掺杂剂密度在本征碱的侧表面提供带阻挡。 栅极可以设置在与发射极相邻的本征基极的顶表面边界上的栅极电介质层上。 栅极被配置为在栅极电介质层的正下方积聚本征基极，从而在本征基极的顶部表面边界提供带状屏障。

公开(公告)号：US20160218062A1

公开(公告)日：2016-07-28

申请号：US14604660

申请日：2015-01-23

Applicant: Texas Instruments Incorporated

Inventor： Rajni J. Aggarwal ,  John P. Campbell ,  Kaiping Liu ,  Weidong Tian

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/31 ,  H01L49/02 ,  H01L21/768 ,  H01L21/02 ,  H01L21/285 ,  H01L21/321 ,  H01L23/528 ,  H01L23/29

CPC classification number: H01L23/5228 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/7684 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit with copper damascene interconnects includes a thin film resistor. Copper damascene metal lines are formed in a first ILD layer. A dielectric layer including an etch stop layer is formed on the first ILD layer and metal lines. Resistor heads of refractory metal are formed in the dielectric layer so that edges of the resistor heads are substantially coplanar with the adjacent dielectric layer. A thin film resistor layer is formed on the dielectric layer, extending onto the resistor heads. A second ILD layer is formed over the dielectric layer and the thin film resistor layer. Copper damascene vias are formed in the second ILD layer, making contact to the metal lines in the first ILD layer. Connections to the resistor heads are provided by the metal lines and/or the vias.

Abstract translation: 具有铜镶嵌互连的集成电路包括薄膜电阻器。 铜镶嵌金属线形成在第一ILD层中。 在第一ILD层和金属线上形成包括蚀刻停止层的电介质层。 难熔金属的电阻头形成在电介质层中，使得电阻头的边缘与相邻的电介质层基本上共面。 在电介质层上形成薄膜电阻层，延伸到电阻头上。 在电介质层和薄膜电阻层上形成第二ILD层。 在第二ILD层中形成铜大马士革通孔，与第一ILD层中的金属线接触。 与电阻头的连接由金属线和/或通孔提供。

公开(公告)号：US20140370621A1

公开(公告)日：2014-12-18

申请号：US14471240

申请日：2014-08-28

Applicant: Texas Instruments Incorporated

Inventor： Rajni J. Aggarwal ,  Scott R. Summerfelt ,  Gul B. Basim ,  Ted S. Moise

IPC: H01L49/02

CPC classification number: H01L28/57 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55

Abstract: An integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. A method for forming an integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer.

Abstract translation: 包含铁电电容器，下伏氢屏障和上覆氢阻挡层的集成电路。 一种用于形成包含铁电电容器，下伏氢屏障和上覆氢阻挡层的集成电路的方法。

公开(公告)号：US20230298946A1

公开(公告)日：2023-09-21

申请号：US18148719

申请日：2022-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abbas Ali ,  Rajni J. Aggarwal ,  Steven J Adler

IPC: H01L21/8249 ,  H01L27/06 ,  H01L29/66 ,  H01L21/763

CPC classification number: H01L21/8249 ,  H01L27/0623 ,  H01L29/66242 ,  H01L21/763

Abstract: An integrated circuit includes a bipolar transistor extending into a [100] surface of a semiconductor substrate having a crystalline lattice. A deep trench surrounds the bipolar transistor and has a path having a plurality of sides. At least one side extends in a direction parallel to a axis of the crystalline lattice.

公开(公告)号：US20230060695A1

公开(公告)日：2023-03-02

申请号：US17462880

申请日：2021-08-31

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali ,  Rajni J. Aggarwal ,  Steven J. Adler ,  Eugene C. Davis

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/265

Abstract: An electronic device comprises a semiconductor substrate including majority carrier dopants of a first conductivity type, a semiconductor surface layer including majority carrier dopants of a second conductivity type, field oxide that extends on the semiconductor surface layer, and an isolation structure. The isolation structure includes a trench that extends through the semiconductor surface layer and into one of the semiconductor substrate and a buried layer of the semiconductor substrate, and polysilicon including majority carrier dopants of the second conductivity type, the polysilicon fills the trench to a side of the semiconductor surface layer.

公开(公告)号：US09006838B2

公开(公告)日：2015-04-14

申请号：US14050935

申请日：2013-10-10

Applicant: Texas Instruments Incorporated

Inventor： Rajni J. Aggarwal ,  Jau-Yuann Yang

IPC: H01L27/092 ,  H01L27/06

CPC classification number: H01L28/20 ,  H01L21/266 ,  H01L21/28035 ,  H01L21/283 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/4916 ,  H01L29/66583 ,  H01L29/6659

Abstract: An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates.

Abstract translation: 一种包含CMOS栅极和反向多晶硅栅极材料电阻器的集成电路，其具有与CMOS栅极的NMOS晶体管的NSD层同时注入并与CMOS栅极的PMOS晶体管的PSD层同时注入的体区，以及 在主体区域上具有与CMOS栅极上的侧壁间隔物分开的材料形成的电阻器硅化物阻挡层。 形成包含CMOS栅极的集成电路和反向掺杂的多晶硅栅极材料电阻器的过程，其将CMOS电极的NMOS晶体管的NSD层同时与电阻体的主体区域并入，并且与PMOS晶体管的PSD层同时 CMOS栅极，并且在与CMOS栅极上的侧壁间隔物分离的材料的主体区域上形成电阻器硅化物阻挡层。