公开(公告)号：US09876071B2

公开(公告)日：2018-01-23

申请号：US14634801

申请日：2015-02-28

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Philip L Hower ,  John Lin ,  Guru Mathur ,  Scott G. Balster ,  Constantin Bulucea ,  Zachary K. Lee ,  Sameer P Pendharkar

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L23/485 ,  H01L29/423

CPC classification number: H01L29/063 ,  H01L23/485 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.

公开(公告)号：US09553011B2

公开(公告)日：2017-01-24

申请号：US14101435

申请日：2013-12-10

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Eugen Mindricelu ,  Sameer Pendharkar ,  Seetharaman Sridhar

IPC: H01L27/088 ,  H01L21/761 ,  H01L27/02

CPC classification number: H01L21/761 ,  H01L21/823481 ,  H01L21/823493 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/0251

Abstract: An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite, conductivity type is formed in the semiconductor material of the first conductivity type. A deep isolation trench is formed in the substrate through the deep well so as separate an unused portion of the deep well from a functional portion of the deep well. The functional portion of the deep well contains an active circuit element of the integrated circuit. The separated portion of the deep well does not contain an active circuit element. A contact region having the second conductivity type and a higher average doping density than the deep well is formed in the separated portion of the deep well. The contact region is connected to a voltage terminal of the integrated circuit.

Abstract translation: 在包含具有第一导电类型的半导体材料的基板上形成集成电路。 在第一导电类型的半导体材料中形成具有第二相对导电类型的深阱。 通过深井在衬底中形成深的隔离沟槽，以将深井的未使用部分与深井的功能部分分开。 深井的功能部分包含集成电路的有源电路元件。 深井的分离部分不包含有源电路元件。 在深井的分离部分中形成具有第二导电类型和比深阱更高的平均掺杂密度的接触区域。 接触区域连接到集成电路的电压端子。

公开(公告)号：US20160254346A1

公开(公告)日：2016-09-01

申请号：US14634801

申请日：2015-02-28

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Philip L. Hower ,  John Lin ,  Guru Mathur ,  Scott G. Balster ,  Constantin Bulucea ,  Zachary K. Lee ,  Sameer P. Pendharkar

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/063 ,  H01L23/485 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.

Abstract translation: 半导体器件包含在漏极漂移区域上具有横向n型漏极漂移区域和p型RESURF区域的LDNMOS晶体管。 RESURF区域延伸到半导体器件的衬底的顶表面。 半导体器件包括电耦合在RESURF区域和LDNMOS晶体管的低电压节点之间的分流器。 分路可以是RESURF层和LDNMOS晶体管的主体之间的衬底中的p型注入层，并且可以与RESURF层同时注入。 分流器可以穿过漏极漂移区域中的从RESURF层到漏极漂移区域下方的衬底的开口。 分路可以包括包括触点和金属互连线的金属互连元件。

公开(公告)号：US20150187934A1

公开(公告)日：2015-07-02

申请号：US14578710

申请日：2014-12-22

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/088 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1037 ,  H01L29/1045 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7831

Abstract: An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a second one current channel is below the buried p-type diffusion.

Abstract translation: 一种具有多个电流通道的LDMOS晶体管的集成电路和方法。 第一电流通道在掩埋的p型扩散之上，并且第二个电流通道在掩埋的p型扩散之下。

公开(公告)号：US10937905B2

公开(公告)日：2021-03-02

申请号：US14286202

申请日：2014-05-23

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Philip L. Hower ,  Sameer P. Pendharkar ,  John Lin ,  Guru Mathur ,  Scott Balster ,  Victor Sinow

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/761 ,  H01L29/10 ,  H01L29/423

Abstract: A semiconductor device includes at least a first transistor including at least a second level metal layer (second metal layer) above a first level metal layer coupled by a source contact to a source region doped with a first dopant type. The second level metal layer is coupled by a drain contact to a drain region doped with the first dopant type. A gate stack is between the source region and drain region having the second level metal layer coupled by a contact thereto. The second level metal layer is coupled by a contact to a first isolation region doped with the second dopant type. The source region and drain region are within the first isolation region. A second isolation region doped with the first dopant type encloses the first isolation region, and is not coupled to the second level metal layer so that it electrically floats.

公开(公告)号：US10601422B2

公开(公告)日：2020-03-24

申请号：US15809291

申请日：2017-11-10

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Philip L. Hower ,  Salvatore Giombanco ,  Filippo Marino ,  Seetharaman Sridhar

IPC: H03K17/687 ,  H01L29/06 ,  H03K19/0185 ,  H01L29/78 ,  H01L29/10 ,  H03K17/12 ,  H01L27/092 ,  H01L21/8238

Abstract: An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.

公开(公告)号：US10304719B2

公开(公告)日：2019-05-28

申请号：US15413118

申请日：2017-01-23

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Eugen Mindricelu ,  Sameer Pendharkar ,  Seetharaman Sridhar

IPC: H01L27/088 ,  H01L21/761 ,  H01L27/02 ,  H01L21/8234 ,  H01L23/528

Abstract: An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite, conductivity type is formed in the semiconductor material of the first conductivity type. A deep isolation trench is formed in the substrate through the deep well so as separate an unused portion of the deep well from a functional portion of the deep well. The functional portion of the deep well contains an active circuit element of the integrated circuit. The separated portion of the deep well does not contain an active circuit element. A contact region having the second conductivity type and a higher average doping density than the deep well is formed in the separated portion of the deep well. The contact region is connected to a voltage terminal of the integrated circuit.

公开(公告)号：US20180108729A1

公开(公告)日：2018-04-19

申请号：US15843444

申请日：2017-12-15

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Philip L. Hower ,  John Lin ,  Guru Mathur ,  Scott G. Balster ,  Constantin Bulucea ,  Zachary K. Lee ,  Sameer P. Pendharkar

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L23/485 ,  H01L29/423

CPC classification number: H01L29/063 ,  H01L23/485 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.

公开(公告)号：US20180097517A1

公开(公告)日：2018-04-05

申请号：US15809291

申请日：2017-11-10

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Philip L. Hower ,  Salvatore Giombanco ,  Filippo Marino ,  Seetharaman Sridhar

IPC: H03K17/687 ,  H01L27/092 ,  H01L29/06 ,  H03K19/0185

CPC classification number: H03K19/018521 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1033 ,  H01L29/7831 ,  H01L29/7835 ,  H03K17/122

Abstract: An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.

公开(公告)号：US20160093612A1

公开(公告)日：2016-03-31

申请号：US14965182

申请日：2015-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/167 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/265 ,  H01L21/324 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L27/088 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1037 ,  H01L29/1045 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7831

Abstract: An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a second one current channel is below the buried p-type diffusion.