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100 条记录 (耗时 0.046 秒)

    Buffer circuit of a semiconductor memory device
    12.
    发明授权
    Buffer circuit of a semiconductor memory device 失效
    半导体存储器件的缓冲电路

    公开(公告)号：US5469402A

    公开(公告)日：1995-11-21

    申请号：US305632

    申请日：1994-09-14

    申请人： Tadaaki Yamauchi ,  Kei Hamade ,  Yoshikazu Morooka

    发明人： Tadaaki Yamauchi ,  Kei Hamade ,  Yoshikazu Morooka

    IPC分类号： G11C11/413 ,  G11C8/06 ,  G11C8/18 ,  G11C11/408

    CPC分类号： G11C8/06 ,  G11C8/18

    摘要： An internal address signal is outputted quickly by connecting nMOS transistors in series to inverters forming a latching circuit of a row address buffer circuit, applying an external row address signal to the gate of a nMOS transistor, applying a delayed activation signal .phi.2 to the gate of the nMOS transistors, grounding the gate of the nMOS transistor, triggering nMOS transistors into complete conduction by the delayed activation signal .phi.2 to reduce the ON resistance. A column address buffer circuit receives a ZCAS circuit by an NOR gate, and an external column address signal by an NAND gate during standby, to prevent a flow of a through current.

    摘要翻译： 通过将nMOS晶体管串联连接到形成行地址缓冲电路的锁存电路的反相器，快速地输出内部地址信号，向nMOS晶体管的栅极施加外部行地址信号，将延迟的激活信号phi2施加到栅极 nMOS晶体管的栅极接地，将nMOS晶体管触发通过延迟的激活信号phi2完全导通，以降低导通电阻。 列地址缓冲电路通过NOR门接收ZCAS电路，在待机期间通过NAND门接收外部列地址信号，以防止通过电流的流动。

    Semiconductor Device Generating Voltage for Temperature Compensation
    14.
    发明申请
    Semiconductor Device Generating Voltage for Temperature Compensation 审中-公开
    用于温度补偿的半导体器件产生电压

    公开(公告)号：US20080238530A1

    公开(公告)日：2008-10-02

    申请号：US12076991

    申请日：2008-03-26

    申请人： Takashi Ito ,  Naruaki Kiriki ,  Tadaaki Yamauchi ,  Minekazu Ono ,  Tsutomu Nagasawa ,  Hidehiko Kuge

    发明人： Takashi Ito ,  Naruaki Kiriki ,  Tadaaki Yamauchi ,  Minekazu Ono ,  Tsutomu Nagasawa ,  Hidehiko Kuge

    IPC分类号： H01L37/00

    CPC分类号： G11C16/30

    摘要： An input transistor unit includes a first transistor having a control electrode to which a reference voltage is supplied. An output transistor unit includes a diode-connected second transistor. At least one of the input transistor unit and the output transistor unit further includes a third transistor that is diode-connected and connected in series with the corresponding first transistor or the second transistor and outputs a current in the same direction as the corresponding transistor does. The number of transistors included in the input transistor unit and the number of transistors included in output transistor unit are different from each other. The size of transistors included in the input transistor unit differs from that of transistors included in the output transistor unit.

    摘要翻译： 输入晶体管单元包括具有供给基准电压的控制电极的第一晶体管。 输出晶体管单元包括二极管连接的第二晶体管。 输入晶体管单元和输出晶体管单元中的至少一个还包括与相应的第一晶体管或第二晶体管串联连接并连接的第三晶体管，并输出与相应的晶体管相同方向的电流。 包括在输入晶体管单元中的晶体管的数量和包括在输出晶体管单元中的晶体管的数量彼此不同。 包括在输入晶体管单元中的晶体管的尺寸与包括在输出晶体管单元中的晶体管的尺寸不同。

    Non-volatile semiconductor memory device
    15.
    发明授权
    Non-volatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US07339833B2

    公开(公告)日：2008-03-04

    申请号：US11481782

    申请日：2006-07-07

    申请人： Yusuke Jono ,  Takashi Kono ,  Tadaaki Yamauchi

    发明人： Yusuke Jono ,  Takashi Kono ,  Tadaaki Yamauchi

    IPC分类号： G11C11/34

    CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0458 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459

    摘要： Using charges accumulated in a capacitance element connected to a drain side node of a memory cell, data is written in accordance with source side injection method. The capacitance value of the capacitance element is changed in accordance with the value of write data. A non-volatile semiconductor memory device allowing writing of multi-valued data at high speed with high precision is achieved.

    摘要翻译： 使用与连接到存储单元的漏极侧节点的电容元件中累积的电荷，根据源侧注入方式写入数据。 电容元件的电容值根据写入数据的值而变化。 实现了以高精度写入多值数据的非易失性半导体存储器件。

    Non-volatile semiconductor memory device allowing efficient programming operation and erasing operation in short period of time
    18.
    发明授权
    Non-volatile semiconductor memory device allowing efficient programming operation and erasing operation in short period of time 有权
    非易失性半导体存储器件允许在短时间内进行有效的编程操作和擦除操作

    公开(公告)号：US07230852B2

    公开(公告)日：2007-06-12

    申请号：US10940812

    申请日：2004-09-15

    申请人： Hidenori Mitani ,  Fumihiko Nitta ,  Tadaaki Yamauchi ,  Taku Ogura

    发明人： Hidenori Mitani ,  Fumihiko Nitta ,  Tadaaki Yamauchi ,  Taku Ogura

    IPC分类号： G11C11/34 ,  G11C16/34

    CPC分类号： G11C29/84 ,  G11C16/10 ,  G11C16/16 ,  G11C16/22 ,  G11C16/30 ,  G11C16/344

    摘要： Until the number of pulse application n reaches 12, as a first-half pulse, a pulse is set to have a width fixed to 2 ms, and its voltage is increased every time. As a latter-half pulse, the pulse is set to have a width fixed to 3 ms and the pulse voltage is increased every time until the maximum voltage is attained. After the maximum voltage is attained, first, the pulse of a width of 3 ms is applied twice, the pulse of a width of 4 ms with the maximum voltage is applied twice, and the pulse of a width of 5 ms with the maximum voltage is applied twice. Even after the maximum voltage is attained, change over time of a threshold voltage can be more linear. Thus, a non-volatile semiconductor memory device allowing efficient programming operation and erasing operation in a short period of time can be provided.

    摘要翻译： 直到脉冲施加次数n达到12为止，作为前半脉冲，脉冲被设置为具有固定为2ms的宽度，并且其电压每次都增加。 作为后半脉冲，脉冲被设置为具有固定为3ms的宽度，并且每次都增加脉冲电压直到达到最大电压。 达到最大电压后，首先施加3 ms宽度的脉冲两次，施加最大电压的4 ms宽度的脉冲两次，最大电压为5 ms的脉冲宽度 被应用两次。 即使在达到最大电压之后，阈值电压的时间变化也可以更线性化。 因此，可以提供允许在短时间段内进行有效的编程操作和擦除操作的非易失性半导体存储器件。

    Semiconductor memory device for improving access time in burst mode
    19.
    发明授权
    Semiconductor memory device for improving access time in burst mode 有权
    用于在突发模式下改善访问时间的半导体存储器件

    公开(公告)号：US07123538B2

    公开(公告)日：2006-10-17

    申请号：US10940777

    申请日：2004-09-15

    申请人： Tadaaki Yamauchi ,  Takashi Kubo

    发明人： Tadaaki Yamauchi ,  Takashi Kubo

    IPC分类号： G11C8/00

    CPC分类号： G11C16/26 ,  G11C7/103 ,  G11C16/32 ,  G11C29/789 ,  G11C29/846

    摘要： A semiconductor memory device is disclosed. A block unit is divided into memory mats based on an internal address. In the case where the internal address is “1”, data are read in ascending order in accordance with a start address from the memory mat, while the internal address is incremented by an address conversion circuit thereby to select a 4-word block including the words next selected from the memory mat. At the same time, the internal address is incremented based on the start address, so that the period for reading each word included in the lowest order of 4-word block can be secured. In the process, the address next to be input can be decoded.

    摘要翻译： 公开了一种半导体存储器件。 块单元基于内部地址被分成存储器块。 在内部地址为“1”的情况下，根据来自存储器堆的开始地址按升序读取数据，而内部地址由地址转换电路递增，从而选择包含 从存储器垫子中选择的单词。 同时，内部地址根据开始地址增加，从而可以确保读取包含在4字块最低位的每个字的周期。 在此过程中，可以对接下来要输入的地址进行解码。

    Semiconductor memory device internally provided with logic circuit which can be readily controlled and controlling method thereof
    20.
    发明授权
    Semiconductor memory device internally provided with logic circuit which can be readily controlled and controlling method thereof 失效
    半导体存储器件内部设置有可以容易地控制和控制方法的逻辑电路

    公开(公告)号：US06931482B2

    公开(公告)日：2005-08-16

    申请号：US09823996

    申请日：2001-04-03

    申请人： Tadaaki Yamauchi ,  Kunihiko Kozaru

    发明人： Tadaaki Yamauchi ,  Kunihiko Kozaru

    IPC分类号： G11C11/407 ,  G06F12/00 ,  G06F12/02 ,  G09C1/00 ,  G11C7/10 ,  G11C7/24 ,  G11C8/00 ,  G11C11/401 ,  G06F13/00

    CPC分类号： G11C7/1006 ,  G06F12/0223 ,  G06F2212/206 ,  G11C7/24

    摘要： If a region designated by an address signal is a logic control region, an interface portion transmits/receives data to/from a register instead of a DRAM. A data signal used at that time is a control command for a logic circuit held in the register or input data for a process in the logic circuit. Depending on the content held in the register, the logic circuit performs, for example, an encryption process or a process which takes for a microcomputer a long time to complete such as an image processing. The result of processing is stored in the register and read in a sequence of reading from the DRAM.

    摘要翻译： 如果由地址信号指定的区域是逻辑控制区域，则接口部分向/从寄存器而不是DRAM发送/接收数据。 此时使用的数据信号是用于逻辑电路中的处理的寄存器中的逻辑电路的控制命令或输入数据。 根据保存在寄存器中的内容，逻辑电路例如执行诸如图像处理等长时间完成的加密处理或微处理器的处理。 处理结果存储在寄存器中并从DRAM读取的顺序读取。