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    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开
    半导体存储器件

    公开(公告)号：US20090080252A1

    公开(公告)日：2009-03-26

    申请号：US12326470

    申请日：2008-12-02

    申请人： Hidenori MITANI ,  Tadaaki YAMAUCHI ,  Taku OGURA

    发明人： Hidenori MITANI ,  Tadaaki YAMAUCHI ,  Taku OGURA

    IPC分类号： G11C7/08 ,  G11C16/26

    CPC分类号： G11C8/10 ,  G11C7/1006 ,  G11C11/56 ,  G11C2211/5641

    摘要： A multi-level semiconductor memory device for storing multi-level data having three or more values is implemented by utilizing a nonvolatile memory device for storing 2-valued data. Identification of successive 16-bit data externally applied is performed with external address bit AA [2], and a storage block is selected with external address bit AA [23]. Upper word data LW and lower word data UW are compressed into byte data of 8 bits, respectively, and stored in a memory cell array.

    摘要翻译： 通过利用用于存储2值数据的非易失性存储器件来实现用于存储具有三个或更多个值的多电平数据的多电平半导体存储器件。 使用外部地址位AA [2]执行外部施加的连续16位数据的识别，并且使用外部地址位AA [23]选择存储块。 高字数据LW和下字数据UW被分别压缩成8位的字节数据，并存储在存储单元阵列中。

    NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE
    8.
    发明申请
    NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 审中-公开
    非挥发性半导体存储器件

    公开(公告)号：US20080019162A1

    公开(公告)日：2008-01-24

    申请号：US11758108

    申请日：2007-06-05

    申请人： Taku OGURA ,  Masaaki Mihara ,  Yoshiki Kawajiri

    发明人： Taku OGURA ,  Masaaki Mihara ,  Yoshiki Kawajiri

    IPC分类号： G11C5/06

    CPC分类号： G11C11/412 ,  G11C14/00 ,  G11C14/0063

    摘要： This non-volatile semiconductor storage device includes a flip-flop in which two inverters, each consisting of a load transistor and a storage transistor connected in series, are cross-connected; and two gate transistors, each respectively connected to a node of the flip-flop on a side thereof. The storage transistors of the inverters are constituted by storage transistors which can be threshold voltage controlled by injection of electrons into the neighborhood of their gates. This non-volatile semiconductor storage device further includes two bit lines, each of which is connected to a respective one of the two gate transistors; a word line which is connected to both of the gate electrodes of the two gate transistors; a first voltage supply line which is connected to the sources of the storage transistors of the inverters; and a second voltage supply line which is connected to the sources of the load transistors of the inverters.

    摘要翻译： 这种非易失性半导体存储器件包括一个触发器，其中每个由串联连接的负载晶体管和存储晶体管组成的两个反相器是交叉连接的; 以及两个栅极晶体管，每个分别在触发器的一侧分别连接到触发器的节点。 反相器的存储晶体管由存储晶体管构成，其可以通过将电子注入其栅极附近来控制阈值电压。 该非易失性半导体存储装置还包括两个位线，每个位线连接到两个栅极晶体管中的相应一个; 连接到两个栅极晶体管的两个栅电极的字线; 连接到逆变器的存储晶体管的源极的第一电源线; 以及与逆变器的负载晶体管的源极连接的第二电压供给线。