公开(公告)号：US07541680B2

公开(公告)日：2009-06-02

申请号：US11509641

申请日：2006-08-25

申请人： Heung-kyu Kwon ,  Se-nyun Kim ,  Tae-hun Kim ,  Jeong-o Ha ,  Hak-kyoon Byun ,  Sung-yong Park

发明人： Heung-kyu Kwon ,  Se-nyun Kim ,  Tae-hun Kim ,  Jeong-o Ha ,  Hak-kyoon Byun ,  Sung-yong Park

IPC分类号： H01L23/12 ,  H01L23/48

CPC分类号： H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Disclosed is a semiconductor device packaging technique that is capable of resolving a problem of instability of bonding wires when stacking a plurality of semiconductor chips. The technique is also capable of realizing a slim, light and small package. The semiconductor device package includes a substrate having a substrate pad on a surface thereof, one or more memory chips stacked on the substrate with each memory chip having a pad connected to a common pin receiving a common signal applied to all the memory chips, an interposer chip stacked on the substrate and having an interconnection wire connected to the memory chip pad, the common pin of each of the memory chips being electrically connected to the interconnection wire via the memory chip pad, and a logic chip stacked on the substrate and having a bypass circuit which electrically connects or disconnects the interconnection wire to or from the substrate pad.

摘要翻译： 公开了一种半导体器件封装技术，其能够在堆叠多个半导体芯片时解决接合线不稳定的问题。 该技术还能够实现纤细，轻巧和小包装。 半导体器件封装包括其表面上具有衬底焊盘的衬底，堆叠在衬底上的一个或多个存储器芯片，每个存储器芯片具有连接到接收施加到所有存储器芯片的公共信号的公共引脚的焊盘，插入器 芯片堆叠在基板上并具有连接到存储器芯片焊盘的互连线，每个存储器芯片的公共引脚经由存储器芯片焊盘电连接到互连线，以及堆叠在基板上的逻辑芯片， 旁路电路，其将互连线电连接到基板焊盘或从基板焊盘断开。

公开(公告)号：US5130944A

公开(公告)日：1992-07-14

申请号：US549942

申请日：1990-07-09

申请人： Ho-sun Chung ,  Sin-jin Kim ,  Tae-hun Kim

发明人： Ho-sun Chung ,  Sin-jin Kim ,  Tae-hun Kim

IPC分类号： G06F7/52 ,  G06F7/535 ,  G06N3/063

CPC分类号： G06F7/535 ,  G06N3/063 ,  G06F2207/4802 ,  G06F2207/5353

摘要： A divider circuit for efficiently and quickly performing a hardware implemented division by adopting a neural network architecture. The circuit includes a series of cascaded subtracter components that complement the divisor input and effectively perform an adder function. The subtracters include a synaptic configuration consisting of PMOS transistors, NMOS transistors, and CMOS inverters. The components are arranged in accordance with the predetermined connection strength assigned to each of the transistors and its respective position in the neural type network arrangement.

摘要翻译： 一种用于通过采用神经网络架构来有效且快速地执行硬件实现的划分的分频器电路。 该电路包括一系列级联减法器组件，用于补偿除数输入并有效执行加法器功能。 减法器包括由PMOS晶体管，NMOS晶体管和CMOS反相器组成的突触配置。 根据分配给每个晶体管的预定连接强度及其在神经型网络布置中的相应位置来布置组件。

公开(公告)号：US08494356B2

公开(公告)日：2013-07-23

申请号：US13271545

申请日：2011-10-12

申请人： Tae-hun Kim ,  Seung-tack Noh

发明人： Tae-hun Kim ,  Seung-tack Noh

IPC分类号： G03B15/03

CPC分类号： G03B17/566 ,  G03B2215/0507 ,  G03B2215/056

摘要： Example pop-up camera flashes are disclosed. A disclosed example pop-up flash of a camera includes a supporting unit; a rotating unit, which is rotatably connected to the supporting unit and is able to rotate between a first position, at which the rotating unit is adjacent to the supporting unit, and a second position, at which the rotating unit is apart from the supporting unit; a sliding unit, which is slidably combined with the rotating unit; a light emitting unit, which is arranged at the sliding unit; a connecting unit, of which a first end is rotatably connected to the sliding unit and a second end is rotatably connected to the supporting unit; and a driving unit, which is connected to the connecting unit and provides a driving force for rotation of the connecting unit.

摘要翻译： 公开了示例性的弹出式照相机闪光。 照相机的公开示例弹出闪光灯包括支撑单元; 旋转单元，其可旋转地连接到支撑单元，并且能够在旋转单元邻近支撑单元的第一位置和第二位置之间旋转，旋转单元与支撑单元分离 ; 滑动单元，其与所述旋转单元可滑动地组合; 布置在滑动单元处的发光单元; 连接单元，其第一端可旋转地连接到滑动单元，第二端可旋转地连接到支撑单元; 以及驱动单元，其连接到连接单元并且提供用于连接单元的旋转的驱动力。

公开(公告)号：US07868443B2

公开(公告)日：2011-01-11

申请号：US12603690

申请日：2009-10-22

申请人： Heung-kyu Kwon ,  Tae-hun Kim ,  Su-chang Lee

发明人： Heung-kyu Kwon ,  Tae-hun Kim ,  Su-chang Lee

IPC分类号： H01L23/02 ,  H01L23/29 ,  H01L23/10 ,  H01L23/48 ,  H01L23/34 ,  H01L23/28 ,  H01L23/31

CPC分类号： H01L25/03 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/552 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A vertical stack type multi-chip package is provided having improved reliability by increasing the grounding performance and preventing the decrease in reliability of the multi-chip package from moisture penetration into a lower semiconductor chip. The vertical stack type multi-chip package comprises an organic substrate having a printed circuit pattern on which a semiconductor chip is mounted. A first semiconductor chip is mounted on a die bonding region of the organic substrate and is electrically connected to the organic substrate through a first wire. A metal stiffener is formed on the first semiconductor chip and connected to the organic substrate by a first ground unit around the first semiconductor chip. An encapsulant is used to seal the first semiconductor chip below the metal stiffener. A second semiconductor chip, which is larger in size than that the first semiconductor chip, is mounted on the metal stiffener and connected by a second ground unit. The second semiconductor chip is connected to the organic substrate by a second wire. A mold resin seals the second semiconductor chip and a solder ball is bonded to a solder ball pad below the organic substrate.

摘要翻译： 通过提高接地性能并防止多芯片封装的湿度渗透到下半导体芯片中的可靠性降低，提供了具有提高的可靠性的垂直堆叠型多芯片封装。 垂直堆叠型多芯片封装包括具有其上安装有半导体芯片的印刷电路图案的有机基板。 第一半导体芯片安装在有机基板的芯片接合区域上，并通过第一导线与有机基板电连接。 在第一半导体芯片上形成金属加强件，并通过第一半导体芯片周围的第一接地单元与有机基板连接。 密封剂用于将金属加强件下方的第一半导体芯片密封。 尺寸大于第一半导体芯片的第二半导体芯片安装在金属加强件上并通过第二接地单元连接。 第二半导体芯片通过第二线连接到有机基板。 模具树脂密封第二半导体芯片，焊球与有机基板下方的焊球焊盘接合。

公开(公告)号：US20080088001A1

公开(公告)日：2008-04-17

申请号：US11898226

申请日：2007-09-11

申请人： Tae-hun Kim ,  Sung-yong Park

发明人： Tae-hun Kim ,  Sung-yong Park

IPC分类号： H01L23/488 ,  H01L21/58

CPC分类号： H01L23/4985 ,  H01L23/49805 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A package on package (POP) and method thereof are provided. The example POP may include a first semiconductor package including a first substrate, the first substrate being a flexible substrate having at least one folded portion, a first semiconductor chip mounted on and electrically connected to the first substrate and a second semiconductor package including a second substrate, at least one second semiconductor chip mounted on and electrically connected to the first substrate, the first and second semiconductor packages being electrically connected between the at least one folded portion of the first substrate and a portion of the second substrate.

摘要翻译： 提供了一种封装（POP）及其方法。 示例POP可以包括包括第一基板的第一半导体封装，第一基板是具有至少一个折叠部分的柔性基板，安装在第一基板上并与之电连接的第一半导体芯片，以及包括第二基板 至少一个第二半导体芯片，其安装在第一基板上并与之电连接，第一和第二半导体封装电连接在第一基板的至少一个折叠部分和第二基板的一部分之间。

公开(公告)号：US20080067659A1

公开(公告)日：2008-03-20

申请号：US11806589

申请日：2007-06-01

申请人： Tae-hun Kim ,  Heung-kyu Kwon

发明人： Tae-hun Kim ,  Heung-kyu Kwon

IPC分类号： H01L23/12 ,  H01L21/50 ,  H01L21/66

CPC分类号： H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/85 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/851 ,  H01L2224/859 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01093 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A stacked semiconductor package may include a wiring substrate. A first semiconductor chip may be disposed on the wiring substrate and wire-bonded to the wiring substrate. An interposer chip may be disposed on the wiring substrate and sire bonded to the wiring substrate. The interposer chip may include a circuit element and a bonding pad being electrically connected. A second semiconductor chip may be disposed on the interposer chip and wire-bonded to the interposer chip. The second semiconductor chip may be electrically connected to the wiring substrate through the interposer chip.

摘要翻译： 堆叠的半导体封装可以包括布线​​基板。 第一半导体芯片可以布置在布线基板上并且引线接合到布线基板。 可以在布线基板上布置插入件芯片，并将其连接到布线基板。 插入器芯片可以包括电连接的电路元件和接合焊盘。 第二半导体芯片可以设置在插入器芯片上并引线接合到插入器芯片。 第二半导体芯片可以通过插入器芯片电连接到布线基板。

公开(公告)号：US20070045828A1

公开(公告)日：2007-03-01

申请号：US11509641

申请日：2006-08-25

申请人： Heung-kyu Kwon ,  Se-nyun Kim ,  Tae-hun Kim ,  Jeong-o Ha ,  Hak-kyoon Byun ,  Sung-yong Park

发明人： Heung-kyu Kwon ,  Se-nyun Kim ,  Tae-hun Kim ,  Jeong-o Ha ,  Hak-kyoon Byun ,  Sung-yong Park

IPC分类号： H01L23/34

CPC分类号： H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Disclosed is a semiconductor device packaging technique that is capable of resolving a problem of instability of bonding wires when stacking a plurality of semiconductor chips. The technique is also capable of realizing a slim, light and small package. The semiconductor device package includes a substrate having a substrate pad on a surface thereof, one or more memory chips stacked on the substrate with each memory chip having a pad connected to a common pin receiving a common signal applied to all the memory chips, an interposer chip stacked on the substrate and having an interconnection wire connected to the memory chip pad, the common pin of each of the memory chips being electrically connected to the interconnection wire via the memory chip pad, and a logic chip stacked on the substrate and having a bypass circuit which electrically connects or disconnects the interconnection wire to or from the substrate pad.

摘要翻译： 公开了一种半导体器件封装技术，其能够在堆叠多个半导体芯片时解决接合线不稳定的问题。 该技术还能够实现纤细，轻巧和小包装。 半导体器件封装包括其表面上具有衬底焊盘的衬底，堆叠在衬底上的一个或多个存储器芯片，每个存储器芯片具有连接到接收施加到所有存储器芯片的公共信号的公共引脚的焊盘，插入器 芯片堆叠在基板上并具有连接到存储器芯片焊盘的互连线，每个存储器芯片的公共引脚经由存储器芯片焊盘电连接到互连线，以及堆叠在基板上的逻辑芯片， 旁路电路，其将互连线电连接到基板焊盘或从基板焊盘断开。

公开(公告)号：US5155699A

公开(公告)日：1992-10-13

申请号：US550503

申请日：1990-07-10

申请人： Ho-sun Chung ,  Sin-jin Kim ,  Tae-hun Kim

发明人： Ho-sun Chung ,  Sin-jin Kim ,  Tae-hun Kim

IPC分类号： G06F7/52 ,  G06F7/535

CPC分类号： G06F7/535 ,  G06F2207/4802 ,  G06F2207/5353

摘要： A divider using neural network configurations comprises a subtractor, a selecting means, a first latch means, a second latch means, a shift register and a control means. The subtractor of the divider comprises plural inverters and plural 3-bit full-adders which are composed of four output lines, an input synapse group, a first bias synapse group, a second bias synapse group, a feedback synapse group, a neuron group and an inverter group.

摘要翻译： 使用神经网络配置的分频器包括减法器，选择装置，第一锁存装置，第二锁存装置，移位寄存器和控制装置。 除法器的减法器包括多个反相器和多个3位全加器，它们由四条输出线，输入突触组，第一偏压突触组，第二偏压突触组，反馈突触组，神经元组和 逆变器组。