公开(公告)号：US20120221880A1

公开(公告)日：2012-08-30

申请号：US13396618

申请日：2012-02-15

申请人： BO-GEUN KIM ,  Kye-hyun Kyung ,  Jae-yong Jeong ,  Seung-hun Choi ,  Seok-cheon Kwon ,  Chul-ho Lee

发明人： BO-GEUN KIM ,  Kye-hyun Kyung ,  Jae-yong Jeong ,  Seung-hun Choi ,  Seok-cheon Kwon ,  Chul-ho Lee

IPC分类号： G06F1/12

CPC分类号： G06F1/12 ,  G06F1/04 ,  G06F1/14 ,  G06F1/3203 ,  G06F1/3225 ,  G06F1/3275 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0683 ,  G06F13/1689 ,  G11C7/222 ,  Y02D10/14

摘要： A memory system comprises a controller that generates a processor clock, and a plurality of memory devices each comprising an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.

摘要翻译： 存储器系统包括产生处理器时钟的控制器和多个存储器件，每个存储器件包括与处理器时钟同步地产生内部时钟的内部时钟发生器，以及与所述处理器时钟同步地执行峰值电流产生操作的存储器 内部时钟，其中至少两个存储器件在不同时间产生它们各自的内部时钟，使得相应的峰值电流产生操作在不同的时间执行。

公开(公告)号：US20100054053A1

公开(公告)日：2010-03-04

申请号：US12614826

申请日：2009-11-09

申请人： Kee-hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

发明人： Kee-hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

IPC分类号： G11C7/00

CPC分类号： G11C5/00 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/222 ,  G11C8/06 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4093

摘要： An integrated circuit memory device may include a memory cell array and a plurality of data input/output pins. The plurality of data input/output pins may be configured to receive data from a memory controller to be written to the memory cell array during a data write operation, and the data input/output pins may be further configured to provide data to the memory controller from the memory cell array during a data read operation. A mode register may be configured to store information defining an operational characteristic of the memory device, and the mode register may be configured to be set using the data input/output bus. Related methods, systems, and additional devices are also discussed.

摘要翻译： 集成电路存储器件可以包括存储单元阵列和多个数据输入/输出引脚。 多个数据输入/输出引脚可以被配置为在数据写入操作期间从存储器控制器接收要写入存储单元阵列的数据，并且数据输入/输出引脚还可以被配置为向存储器控制器 在数据读取操作期间从存储单元阵列。 模式寄存器可以被配置为存储定义存储器件的操作特性的信息，并且模式寄存器可以被配置为使用数据输入/输出总线进行设置。 还讨论了相关方法，系统和附加设备。

公开(公告)号：US07457192B2

公开(公告)日：2008-11-25

申请号：US11607311

申请日：2006-12-01

申请人： Kye-hyun Kyung

发明人： Kye-hyun Kyung

IPC分类号： G11C8/00

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1093

摘要： The present invention relates to a synchronous semiconductor memory device with double data rate, and more particularly, to a synchronous semiconductor memory device for inputting and outputting data using a free-running clock and inserting a preamble indicative of start of data into the outputted data. A semiconductor memory device of the present invention receives a data read command from the exterior of the memory device in response to a predetermined clock signal inputted from the exterior, and outputting data including a preamble in response to the clock signal.

摘要翻译： 本发明涉及具有双倍数据速率的同步半导体存储器件，更具体地说，涉及一种使用自由运行时钟输入和输出数据的同步半导体存储器件，并将表示数据开始的前导码输入到输出数据中。 本发明的半导体存储器件响应于从外部输入的预定时钟信号从存储器件的外部接收数据读取命令，并且响应于时钟信号输出包括前置码的数据。

公开(公告)号：US20070049235A1

公开(公告)日：2007-03-01

申请号：US11509732

申请日：2006-08-25

申请人： Kye-hyun Kyung

发明人： Kye-hyun Kyung

IPC分类号： H04B1/26

CPC分类号： H04L25/0272 ,  H04L25/0276

摘要： A signal transmission apparatus may transmit and receive a differential signal using transmission lines. The apparatus may include a transmitter and a receiver. The transmitter may transmit a mixed signal obtained by mixing the differential signal with a single ended signal. The receiver may restore the differential signal and the single ended signal from the mixed signal. An edge of the single ended signal may have a phase difference of about 90° with an edge of the differential signal. The signal transmission apparatus and method may transmit two signals through a single channel to reduce a circuit area.

摘要翻译： 信号发送装置可以使用传输线路发送和接收差分信号。 该装置可以包括发射机和接收机。 发射机可以发送通过将差分信号与单端信号混合而获得的混合信号。 接收机可以从混合信号中恢复差分信号和单端信号。 单端信号的边沿可以与差分信号的边缘具有约90°的相位差。 信号发送装置和方法可以通过单个信道发送两个信号以减少电路面积。

公开(公告)号：US20050007835A1

公开(公告)日：2005-01-13

申请号：US10916156

申请日：2004-08-11

申请人： Kee-hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

发明人： Kee-hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

IPC分类号： G11C7/10 ,  G11C11/4093 ,  G11C7/00

CPC分类号： G11C5/00 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/222 ,  G11C8/06 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4093

摘要： A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation. An enable signal may be provided from the memory controller to a second one of the integrated circuit memory devices over a signal line between the memory controller and the second integrated circuit memory device to thereby enable implementation of the mode register set command for the second integrated circuit memory device during the mode register set operation. Moreover, the disable signal may not be provided to the second integrated circuit memory device during the mode register set operation, and the enable signal may not be provided to the first integrated circuit memory device during the mode register set operation. Related systems, devices and additional methods are also discussed.

摘要翻译： 存储器模块可以包括通过相同的命令/地址总线耦合到存储器控制器的多个存储器件。 控制这种存储器模块的方法可以包括在模式寄存器设置操作期间通过命令/地址总线从存储器控制器向每个集成电路存储器件提供模式寄存器设置命令。 可以通过存储器控制器和第一集成电路存储器件之间的信号线从存储器控制器向集成电路存储器件中的第一个提供禁止信号，从而禁止第一集成电路的模式寄存器设置命令的实现 存储器件在模式寄存器设置操作期间。 可以通过存储器控制器和第二集成电路存储器件之间的信号线从存储器控制器向集成电路存储器件中的第二个提供使能信号，从而能够实现第二集成电路的模式寄存器设置命令 存储器件在模式寄存器设置操作期间。 此外，在模式寄存器设置操作期间，禁止信号可能不被提供给第二集成电路存储器件，并且在模式寄存器设置操作期间可以不向第一集成电路存储器件提供使能信号。 还讨论了相关系统，设备和附加方法。

公开(公告)号：US6046947A

公开(公告)日：2000-04-04

申请号：US198702

申请日：1998-11-24

申请人： Joon-wan Chai ,  Kye-hyun Kyung

发明人： Joon-wan Chai ,  Kye-hyun Kyung

IPC分类号： G01R31/28 ,  G01R31/26 ,  G11C11/401 ,  G11C29/00 ,  G11C29/32 ,  G11C29/48 ,  G11C7/00

CPC分类号： G11C29/32 ,  G11C29/48

摘要： Integrated circuit memory devices include test mode control circuits to more efficiently route test data to a fewer number of output pins during test mode operation. The memory device may include first and second memory arrays having first and second pluralities of data lines electrically coupled thereto, respectively. First and second pluralities of latch units are also provided. The first plurality of latch units are electrically coupled together in series as a first pipelined latch unit and electrically coupled in parallel to the first memory array by the first plurality of data lines. The second plurality of latch units are electrically coupled together in series as a second pipelined latch unit and electrically coupled in parallel to the second memory array by the second plurality of data lines. A preferred test mode control circuit electrically couples an output of the first pipelined latch unit to an input of the second pipelined latch unit, in response to a test mode control signal (.phi.DAE). This test mode control circuit enables the transfer of data from the first pipelined latch unit to the second pipelined latch unit during direct access test mode reading operations. This data can then be transferred from the first pipelined latch unit to an output driver and then serially transmitted to a single input/output pin. Additional memory arrays within the memory device may also be linked together during test mode operation to improve testing efficiency when multiple memory devices are tested simultaneously in a memory testing apparatus.

摘要翻译： 集成电路存储器件包括测试模式控制电路，以便在测试模式操作期间将测试数据更有效地路由到较少数量的输出引脚。 存储器件可以包括分别与其电耦合的第一和第二多条数据线的第一和第二存储器阵列。 还提供了第一和第二多个闩锁单元。 第一组多个锁存单元串联电耦合在一起作为第一流水线锁存单元，并由第一多个数据线电耦合到第一存储器阵列。 第二组多个锁存单元作为第二流水线锁存单元串联电耦合在一起，并由第二多个数据线电耦合到第二存储器阵列。 响应于测试模式控制信号（phi DAE），优选的测试模式控制电路将第一流水线锁存单元的输出电耦合到第二流水线锁存单元的输入。 该测试模式控制电路使得能够在直接访问测试模式读取操作期间将数据从第一流水线锁存单元传送到第二流水线锁存单元。 然后，该数据可以从第一流水线锁存单元传送到输出驱动器，然后串行传输到单个输入/输出引脚。 在测试模式操作期间，存储器装置内的附加存储器阵列也可以连接在一起，以便在存储器测试装置中同时测试多个存储器件时提高测试效率。

公开(公告)号：US5783935A

公开(公告)日：1998-07-21

申请号：US636116

申请日：1996-04-22

申请人： Kye-hyun Kyung

发明人： Kye-hyun Kyung

IPC分类号： G05F1/10 ,  G05F1/46 ,  G05F1/56 ,  G05F1/613 ,  G05F3/24 ,  G05F3/16

CPC分类号： G05F3/242 ,  G05F1/465 ,  Y10S323/907

摘要： A reference voltage generating circuit has a divider circuit for decreasing a received external power-supply voltage and for providing the decreased voltage at a reference voltage output terminal. A PMOS transistor clamps the reference voltage at a predetermined voltage level, one end thereof being coupled to the reference voltage output terminal and the other end being coupled to a ground. A compensating unit adjusts the substrate voltage of the PMOS transistor to compensate for level variations of the reference voltage in response to the level variations. Thus, variations in the reference voltage caused by changes in processing variables are compensated, thereby maintaining the reference voltage at a predetermined level.

摘要翻译： 参考电压产生电路具有用于减小接收到的外部电源电压并用于在参考电压输出端子处提供降低的电压的分压电路。 PMOS晶体管将参考电压钳位在预定电压电平，其一端耦合到参考电压输出端，另一端耦合到地。 补偿单元调整PMOS晶体管的衬底电压，以补偿参考电压响应于电平变化的电平变化。 因此，补偿了由处理变量变化引起的参考电压的变化，从而将参考电压保持在预定的水平。

公开(公告)号：US20110298011A1

公开(公告)日：2011-12-08

申请号：US13151691

申请日：2011-06-02

申请人： Sang-bo Lee ,  Kye-hyun Kyung

发明人： Sang-bo Lee ,  Kye-hyun Kyung

IPC分类号： H01L25/03

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/108 ,  H01L2224/0557 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01322 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2224/05552

摘要： Example embodiments relate to a semiconductor memory device and a system in which a plurality of semiconductor layers are stacked on each other. A 3-dimensional (3D) semiconductor memory device may include a plurality of semiconductor layers that are stacked on each other. The plurality of semiconductor layers may have the same memory cell structure. The 3D semiconductor memory device may include a first memory region including at least one semiconductor layer for storing system data and a second memory region including at least one semiconductor layer for storing data aside from the system data. The system data may include at least one piece of data selected from the group consisting of a booting code, a system code, and application software.

摘要翻译： 示例性实施例涉及半导体存储器件和其中多个半导体层彼此堆叠的系统。 三维（3D）半导体存储器件可以包括堆叠在一起的多个半导体层。 多个半导体层可以具有相同的存储单元结构。 3D半导体存储器件可以包括包括用于存储系统数据的至少一个半导体层的第一存储器区域和包括用于存储除了系统数据之外的数据的至少一个半导体层的第二存储器区域。 系统数据可以包括从由引导代码，系统代码和应用软件组成的组中选择的至少一条数据。

公开(公告)号：US20090059680A1

公开(公告)日：2009-03-05

申请号：US12260373

申请日：2008-10-29

申请人： Kee-Hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

发明人： Kee-Hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

IPC分类号： G11C7/00 ,  G11C8/00 ,  G11C8/18

CPC分类号： G11C5/00 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/222 ,  G11C8/06 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4093

摘要： A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation. An enable signal may be provided from the memory controller to a second one of the integrated circuit memory devices over a signal line between the memory controller and the second integrated circuit memory device to thereby enable implementation of the mode register set command for the second integrated circuit memory device during the mode register set operation. Moreover, the disable signal may not be provided to the second integrated circuit memory device during the mode register set operation, and the enable signal may not be provided to the first integrated circuit memory device during the mode register set operation. Related systems, devices and additional methods are also discussed.

摘要翻译： 存储器模块可以包括通过相同的命令/地址总线耦合到存储器控制器的多个存储器件。 控制这种存储器模块的方法可以包括在模式寄存器设置操作期间通过命令/地址总线从存储器控制器向每个集成电路存储器件提供模式寄存器设置命令。 可以通过存储器控制器和第一集成电路存储器件之间的信号线从存储器控制器向集成电路存储器件中的第一个提供禁止信号，从而禁止第一集成电路的模式寄存器设置命令的实现 存储器件在模式寄存器设置操作期间。 可以通过存储器控制器和第二集成电路存储器件之间的信号线从存储器控制器向集成电路存储器件中的第二个提供使能信号，从而能够实现第二集成电路的模式寄存器设置命令 在模式寄存器设置操作期间的存储器件。 此外，在模式寄存器设置操作期间，禁止信号可能不被提供给第二集成电路存储器件，并且在模式寄存器设置操作期间可以不向第一集成电路存储器件提供使能信号。 还讨论了相关系统，设备和附加方法。

公开(公告)号：US07477067B2

公开(公告)日：2009-01-13

申请号：US11498928

申请日：2006-08-03

申请人： Kye-hyun Kyung

发明人： Kye-hyun Kyung

IPC分类号： G01R31/02 ,  G01R31/26

CPC分类号： G01R31/2856 ,  G01R31/2879

摘要： A semiconductor integrated circuit and method for burn-in-testing are provided that uniformly apply stress to elements of the semiconductor integrated circuit in a burn-in test mode, even when packaged. The semiconductor integrated circuit may include a transmission control unit that transmits an operation signal in a normal operating mode and blocks the operation signal in the test mode; and a test control unit that sequentially outputs a first signal and a second signal to an input/output (I/O) circuit in the test mode.

摘要翻译： 提供了一种用于老化测试的半导体集成电路和方法，即使在封装时，也可以在老化测试模式下均匀地将应力施加于半导体集成电路的元件。 半导体集成电路可以包括传输控制单元，其以正常操作模式发送操作信号并且在测试模式中阻止操作信号; 以及测试控制单元，其在测试模式中顺序地将第一信号和第二信号输出到输入/输出（I / O）电路。