公开(公告)号：US11251142B2

公开(公告)日：2022-02-15

申请号：US16881013

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hsiang Lin ,  Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Shin-Puu Jeng ,  Arunima Banerjee

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L21/683 ,  H01L25/10 ,  H01L23/31 ,  H01L25/065

Abstract: A package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements. The fabrication methods for forming a package structure are provided.

公开(公告)号：US12094828B2

公开(公告)日：2024-09-17

申请号：US17126881

申请日：2020-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Che-Chia Yang ,  Chia-Kuei Hsu ,  Po-Yao Lin ,  Shin-Puu Jeng ,  Chia-Hsiang Lin

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/5384 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/76802 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/14

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line including a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes depositing a conductive material into the via opening to form a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, and the second via is offset from a center line of the conductive bump.

公开(公告)号：US11855008B2

公开(公告)日：2023-12-26

申请号：US17818729

申请日：2022-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Che-Chia Yang ,  Chin-Hua Wang ,  Po-Yao Lin ,  Shin-Puu Jeng ,  Chia-Hsiang Lin

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/35121

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

公开(公告)号：US20230307338A1

公开(公告)日：2023-09-28

申请号：US17706313

申请日：2022-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Tung Yu ,  Chia-Hsiang Lin ,  Chi-Pu Lin ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L24/73 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0655 ,  H01L25/105 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/24 ,  H01L2224/24226 ,  H01L2224/73204 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L23/49816

Abstract: A method includes forming a redistribution structure, wherein forming the redistribution structure includes forming a first conductive material on a portion of a first seed layer, forming a mask over the first seed layer and the first conductive material, wherein an opening in the mask at least partially exposes the first conductive material, forming a first conductive via in the opening, etching portions of the first seed layer using the first conductive material as an etching mask, depositing a first insulating layer over the first conductive via, the first conductive material and remaining portions of the first seed layer, and etching the first insulating layer such that a portion of the first conductive via protrudes above a top surface of the first insulating layer, and attaching a first die to the redistribution structure using first electrical connectors.

公开(公告)号：US11107801B2

公开(公告)日：2021-08-31

申请号：US16233653

申请日：2018-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Po-Yao Lin ,  Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Chia-Hsiang Lin

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L21/32 ,  H01L25/00 ,  G03F7/20 ,  H01L21/033

Abstract: A package structure and method for forming the same are provided. The package structure includes a first redistribution structure formed over a substrate, and the first redistribution structure includes a first conductive line, a second conductive line and a first overlapping conductive line between the first conductive line and the second conductive line. The first conductive line has a first width, the second conductive line which is parallel to the first conductive line has a second width, and the overlapping conductive line has a third width which is greater than the first width and the second width. The package structure includes a first package unit formed over the first redistribution structure, and the first package unit includes a first semiconductor die and a first die stack, and the first semiconductor die has a different function than the first die stack.