公开(公告)号：US20220077384A1

公开(公告)日：2022-03-10

申请号：US17525927

申请日：2021-11-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Ya-Jui TSOU ,  Zong-You LUO ,  Chee-Wee LIU ,  Shao-Yu LIN ,  Liang-Chor CHUNG ,  Chih-Lin WANG

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16

Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer, a spacer layer over the pinned layer, a reference layer over the spacer layer, and a tunnel barrier layer over the reference layer. The SOT layer has a top surface substantially coplanar with a top surface of the tunnel barrier layer of the memory stack. The free layer interconnects the SOT layer and the tunnel barrier layer.

公开(公告)号：US20210193911A1

公开(公告)日：2021-06-24

申请号：US16721789

申请日：2019-12-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Hsiang TSENG ,  Chih-Lin WANG ,  Yi-Huang WU

IPC: H01L43/08 ,  H01L43/12 ,  H01L43/02

Abstract: A memory device includes a substrate, an etch stop layer, a protective layer, and a resistance switching element. The substrate has a memory region and a logic region, and includes a metallization pattern therein. The etch stop layer is over the substrate, and has a first portion over the memory region and a second portion over the logic region. The protective layer covers the first portion of the etch stop layer. The protective layer does not cover the second portion of the etch stop layer. The resistance switching element is over the memory region, and the resistance switching element is electrically connected to the metallization pattern through the etch stop layer and the protective layer.

公开(公告)号：US20200058756A1

公开(公告)日：2020-02-20

申请号：US16665296

申请日：2019-10-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ruei YEH ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/45 ,  H01L29/423 ,  H01L29/40 ,  H01L21/768 ,  H01L21/02 ,  H01L29/49 ,  H01L29/66

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a metal gate electrode structure and an insulating layer over the semiconductor substrate. The insulating layer surrounds the metal gate electrode structure. The method includes nitrifying a first top portion of the metal gate electrode structure to form a metal nitride layer over the metal gate electrode structure.

公开(公告)号：US20180342514A1

公开(公告)日：2018-11-29

申请号：US16055526

申请日：2018-08-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Wei LIN ,  Chih-Lin WANG ,  Kang-Min KUO ,  Cheng-Wei LIAN

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/823842 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656

Abstract: Methods for forming a semiconductor structure are provided. The method includes forming a first dummy gate structure and forming first spacers over a sidewall of the first dummy gate structure. The method includes removing the first dummy gate structure to form a first trench between the first spacers and forming a first capping layer in the first trench. A first portion of the first capping layer covers a sidewall of the first trench and a second portion of the first capping layer covers a bottom surface of the first trench. The method further includes oxidizing a sidewall of the first portion of the first capping layer and a top surface of the second portion of the first capping layer to form a first capping oxide layer and forming a first work function metal layer and forming a first gate electrode layer over the first work function metal layer.

公开(公告)号：US20180174962A1

公开(公告)日：2018-06-21

申请号：US15893538

申请日：2018-02-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Sheng ZHENG ,  Chih-Lin WANG

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnection structure includes a first dielectric layer, a first conductor, an etch stop layer, and a second dielectric layer. The first conductor is partially in the first dielectric layer and having a portion protruding from the first dielectric layer. The etch stop layer is on the first dielectric layer and covering the protruding portion of the first conductor. The second dielectric layer is on the etch stop layer. A bottom surface of the second dielectric layer has a portion in a position lower than a top of the first conductor.

公开(公告)号：US20170221758A1

公开(公告)日：2017-08-03

申请号：US15489947

申请日：2017-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Cheng LIN ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/311 ,  H01L23/522 ,  H01L21/02

CPC classification number: H01L21/76877 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first dielectric layer and a first conductive structure over a substrate. The first dielectric layer surrounds the first conductive structure. The method includes forming a second dielectric layer over the first dielectric layer. The second dielectric layer has an opening exposing the first conductive structure. The method includes forming a seal layer over the first conductive structure and an inner wall of the opening. The seal layer is in direct contact with the first dielectric layer and the second dielectric layer, and the seal layer includes a dielectric material comprising an oxygen compound. The method includes removing the seal layer over the first conductive structure. The method includes filling a second conductive structure into the opening.

公开(公告)号：US20170148665A1

公开(公告)日：2017-05-25

申请号：US15425639

申请日：2017-02-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Wen-Jia HSIEH ,  Chih-Lin WANG ,  Chia-Der CHANG

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/285 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/76814 ,  H01L21/02244 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a metal gate stack formed over the semiconductor substrate. The semiconductor device also includes an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the metal gate stack includes a metal gate electrode. The semiconductor device further includes a metal oxide structure formed over the insulating layer and in direct contact with the insulating layer. The metal oxide structure includes an oxidized material of the metal gate electrode.

公开(公告)号：US20150084137A1

公开(公告)日：2015-03-26

申请号：US14037881

申请日：2013-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Jia HSIEH ,  Chih-Lin WANG ,  Chia-Der CHANG

IPC: H01L21/28 ,  H01L21/285 ,  H01L29/417 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/76814 ,  H01L21/02244 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a metal gate stack formed over the semiconductor substrate. The semiconductor device also includes an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the metal gate stack includes a metal gate electrode. The semiconductor device further includes a metal oxide structure formed over the insulating layer and in direct contact with the insulating layer. The metal oxide structure includes an oxidized material of the metal gate electrode.

Abstract translation: 提供了用于形成半导体器件的机构的实施例。 半导体器件包括形成在半导体衬底上的半导体衬底和金属栅极叠层。 半导体器件还包括形成在半导体衬底上并围绕金属栅堆叠的绝缘层，其中金属栅叠层包括金属栅电极。 半导体器件还包括形成在绝缘层上并与绝缘层直接接触的金属氧化物结构。 金属氧化物结构包括金属栅电极的氧化材料。

公开(公告)号：US20240237545A1

公开(公告)日：2024-07-11

申请号：US18608365

申请日：2024-03-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Hsiang TSENG ,  Chih-Lin WANG ,  Yi-Huang WU

IPC: H10N50/10 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10N50/10 ,  H10N50/01 ,  H10N50/80

Abstract: A memory device includes a bottom electrode, a resistance switching element over the bottom electrode, a top electrode over the resistance switching element, and a dielectric layer. The dielectric layer surrounds the bottom electrode, the resistance switching element, and the top electrode. The resistance switching element has a first portion between the top electrode and the dielectric layer.

公开(公告)号：US20230360686A1

公开(公告)日：2023-11-09

申请号：US18352872

申请日：2023-07-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Zong-You LUO ,  Ya-Jui TSOU ,  Chee-Wee LIU ,  Shao-Yu LIN ,  Liang-Chor CHUNG ,  Chih-Lin WANG

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: G11C11/161 ,  H10B61/00 ,  H10B61/20 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.