公开(公告)号：US20170250268A1

公开(公告)日：2017-08-31

申请号：US15054091

申请日：2016-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Chii-Ming Wu ,  Chi-Cherng Jeng

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/10 ,  H01L29/49 ,  H01L21/311 ,  H01L21/283 ,  H01L29/78 ,  H01L29/06 ,  H01L21/306 ,  H01L21/3213

CPC classification number: H01L29/66818 ,  H01L21/28238 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A FinFET includes a semiconductor substrate, a plurality of insulators, a gate stack, and a strained material. The semiconductor substrate includes at least one semiconductor fin thereon. The semiconductor fin includes source/drain regions and a channel region, and a width of the source/drain regions is larger than a width of the channel region. The insulators are disposed on the semiconductor substrate and the semiconductor fin is sandwiched by the insulators. The gate stack is located over the channel region of the semiconductor fin and over portions of the insulators. The strained material covers the source/drain regions of the semiconductor fin. In addition, a method for fabricating the FinFET is provided.

公开(公告)号：US20170250089A1

公开(公告)日：2017-08-31

申请号：US15054142

申请日：2016-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Huang Kuo ,  Chia-Pin Lo ,  Wei-Barn Chen ,  Chen-Chieh Chiang ,  Chii-Ming Wu ,  Chi-Cherng Jeng

IPC: H01L21/3115 ,  H01L27/092 ,  H01L21/32 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/3105

CPC classification number: H01L27/0922 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/3105 ,  H01L21/823821 ,  H01L27/0924

Abstract: Semiconductor devices and manufacturing method of the same are disclosed. A semiconductor device includes a substrate, a p-type MOS transistor, an n-type MOS transistor and a cured flowable oxide layer. The substrate includes a first region and a second region. The p-type MOS transistor is in the first region. The n-type MOS transistor is in the second region. The cured flowable oxide layer covers the p-type MOS transistor and the n-type MOS transistor, wherein a first strain of the cured flowable oxide layer applying to the p-type MOS transistor is different from a second strain of the cured flowable oxide layer applying to the n-type MOS transistor, and the difference therebetween is greater than 0.002 Gpa.

公开(公告)号：US11923235B2

公开(公告)日：2024-03-05

申请号：US17877824

申请日：2022-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Chii-Ming Wu ,  Sen-Hong Syue ,  Cheng-Po Chau

IPC: H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L27/105 ,  H01L27/146

CPC classification number: H01L21/76229 ,  H01L21/76232 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/785 ,  H01L27/105 ,  H01L27/1463

Abstract: A method includes forming a first trench and a second trench in a semiconductor substrate; forming a first mask over the semiconductor substrate, wherein the first mask is disposed in a first portion of the first trench and exposes the second trench and a second portion of the first trench; after forming the first mask, deepening the second trench and the second portion of the first trench; after deepening the second trench and the second portion of the first trench, removing the first mask; and after removing the first mask, filling a dielectric material in both the first and second trenches.

公开(公告)号：US20210159407A1

公开(公告)日：2021-05-27

申请号：US17142591

申请日：2021-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hai-Dang Trinh ,  Chii-Ming Wu ,  Hsing-Lien Lin ,  Fa-Shen Jiang

IPC: H01L45/00 ,  H01L27/24 ,  H01L23/528

Abstract: In some embodiments, the present disclosure relates to method of forming an integrated chip. The method includes forming a bottom electrode structure over one or more interconnect layers disposed within one or more stacked inter-level dielectric (ILD) layers over a substrate. The bottom electrode structure has an upper surface having a noble metal. A diffusion barrier film is formed over the bottom electrode structure. A data storage film is formed onto the diffusion barrier film, and a top electrode structure is over the data storage film. The top electrode structure, the data storage film, the diffusion barrier film, and the bottom electrode structure are patterned to define a memory device.

公开(公告)号：US20210074805A1

公开(公告)日：2021-03-11

申请号：US16567247

申请日：2019-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Lien Lin ,  Chii-Ming Wu ,  Hai-Dang Trinh ,  Fa-Shen Jiang

IPC: H01L49/02 ,  H01L23/522

Abstract: Various embodiments of the present disclosure are directed towards a metal-insulator-metal (MIM) capacitor including a diffusion barrier layer. A bottom electrode overlies a substrate. A capacitor dielectric layer overlies the bottom electrode. A top electrode overlies the capacitor dielectric layer. The top electrode includes a first top electrode layer, a second top electrode layer, and a diffusion barrier layer disposed between the first and second top electrode layers.

公开(公告)号：US20210066587A1

公开(公告)日：2021-03-04

申请号：US16788611

申请日：2020-02-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hai-Dang Trinh ,  Chii-Ming Wu ,  Cheng-Yuan Tsai ,  Tzu-Chung Tsai ,  Fa-Shen Jiang

IPC: H01L45/00

Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a data storage structure. A top electrode overlies a bottom electrode. The data storage structure is disposed between the top electrode and the bottom electrode. The data storage structure includes a first data storage layer, a second data storage layer, and a third data storage layer. The second data storage layer is disposed between the first and third data storage layers. The second data storage layer has a lower bandgap than the third data storage layer. The first data storage layer has a lower bandgap than the second data storage layer.

公开(公告)号：US10910560B2

公开(公告)日：2021-02-02

申请号：US16232342

申请日：2018-12-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hai-Dang Trinh ,  Chii-Ming Wu ,  Hsing-Lien Lin ,  Fa-Shen Jiang

IPC: H01L45/00 ,  H01L27/24 ,  H01L23/528

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over one or more interconnect layers and a diffusion barrier layer is arranged over the bottom electrode. A data storage layer is separated from the bottom electrode by the diffusion barrier layer. A top electrode is over the data storage layer.

公开(公告)号：US10818544B2

公开(公告)日：2020-10-27

申请号：US16111605

申请日：2018-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Lien Lin ,  Chii-Ming Wu ,  Hai-Dang Trinh ,  Fa-Shen Jiang

IPC: H01L21/768 ,  H01L49/02 ,  H01L43/02 ,  H01L23/535 ,  H01L23/532 ,  H01L21/285 ,  H01L45/00 ,  H01L43/08 ,  H01L43/12

Abstract: The present disclosure relates to an integrated circuit (IC) comprising an adhesion layer to enhance adhesion of an electrode. In some embodiments, the IC comprises a via dielectric layer, an adhesion layer, and a first electrode. The adhesion layer overlies the via dielectric layer, and the first electrode overlies and directly contacts the adhesion layer. The adhesion layer has a first surface energy at an interface at which the first electrode contacts the adhesion layer, and the first electrode has a second surface energy at the interface. Further, the first surface energy is greater than the second surface energy to promote adhesion. The present disclosure also relates to a method for forming the IC.

公开(公告)号：US20200098985A1

公开(公告)日：2020-03-26

申请号：US16232342

申请日：2018-12-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hai-Dang Trinh ,  Chii-Ming Wu ,  Hsing-Lien Lin ,  Fa-Shen Jiang

IPC: H01L45/00 ,  H01L27/24 ,  H01L23/528

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over one or more interconnect layers and a diffusion barrier layer is arranged over the bottom electrode. A data storage layer is separated from the bottom electrode by the diffusion barrier layer. A top electrode is over the data storage layer.

公开(公告)号：US10535568B2

公开(公告)日：2020-01-14

申请号：US16233243

申请日：2018-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Han Tsao ,  Chii-Ming Wu ,  Cheng-Yuan Tsai ,  Yi-Huan Chen

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/49 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/51

Abstract: Some embodiments relate to an integrated circuit including a semiconductor substrate including a multi-voltage device region. A first pair of source/drain regions are spaced apart from one another by a first channel region. A dielectric layer is disposed over the first channel region. A barrier layer is disposed over the dielectric layer. A fully silicided gate is disposed over the first channel region and is vertically separated from the semiconductor substrate by a work function tuning layer. The work function tuning layer separates the fully silicided gate from the barrier layer.