公开(公告)号：US11978810B2

公开(公告)日：2024-05-07

申请号：US17324402

申请日：2021-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Liang-Yu Su ,  Chih-Wen Yao ,  Hsiao-Chin Tuan ,  Ming-Ta Lei

IPC: H01L29/66 ,  H01L27/08 ,  H01L29/06 ,  H01L29/93

CPC classification number: H01L29/93 ,  H01L27/0808 ,  H01L29/063 ,  H01L29/66174

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a varactor comprising a reduced surface field (RESURF) region. The method includes forming a drift region having a first doping type within a substrate. A RESURF region having a second doping type is formed within the substrate such that the RESURF region is below the drift region. A gate structure is formed on the substrate. A pair of contact regions is formed within the substrate on opposing sides of the gate structure. The contact regions respectively abut the drift region and have the first doping type, and wherein the first doping type is opposite the second doping type.

公开(公告)号：US11133226B2

公开(公告)日：2021-09-28

申请号：US16169220

申请日：2018-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Chien-Chih Chou ,  Ta-Wei Lin ,  Hsiao-Chin Tuan ,  Alexander Kalnitsky ,  Kong-Beng Thei ,  Chia-Hong Wu

IPC: H01L29/49 ,  H01L21/3213 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/51 ,  H01L21/3105 ,  H01L29/08 ,  H01L27/092 ,  H01L29/45

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a fully silicided (FUSI) gated device, the method including: forming a masking layer onto a gate structure over a substrate, the gate structure comprising a polysilicon layer. Forming a first source region and a first drain region on opposing sides of the gate structure within the substrate, the gate structure is formed before the first source and drain regions. Performing a first removal process to remove a portion of the masking layer and expose an upper surface of the polysilicon layer. The first source and drain regions are formed before the first removal process. Forming a conductive layer directly contacting the upper surface of the polysilicon layer. The conductive layer is formed after the first removal process. Converting the conductive layer and polysilicon layer into a FUSI layer. The FUSI layer is thin and uniform in thickness.

公开(公告)号：US11018266B2

公开(公告)日：2021-05-25

申请号：US16434381

申请日：2019-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Liang-Yu Su ,  Chih-Wen Yao ,  Hsiao-Chin Tuan ,  Ming-Ta Lei

IPC: H01L29/93 ,  H01L27/08 ,  H01L29/66 ,  H01L29/06

Abstract: Various embodiments of the present disclosure are directed towards a varactor comprising a reduced surface field (RESURF) region. In some embodiments, the varactor includes a drift region, a gate structure, a pair of contact regions, and a RESURF region. The drift region is within a substrate and has a first doping type. The gate structure overlies the drift region. The contact regions are within the substrate and overlie the drift region. Further, the contact regions have the first doping type. The gate structure is laterally sandwiched between the contact regions. The RESURF region is in the substrate, below the drift region, and has a second doping type. The second doping type is opposite the first doping type. The RESURF region aids in depleting the drift region under the gate structure, which decreases the minimum capacitance of the varactor and increases the tuning range of the varactor.

公开(公告)号：US10790279B2

公开(公告)日：2020-09-29

申请号：US16656756

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kong-Beng Thei ,  Chien-Chih Chou ,  Fu-Jier Fan ,  Hsiao-Chin Tuan ,  Yi-Huan Chen ,  Alexander Kalnitsky ,  Yi-Sheng Chen

IPC: H01L27/088 ,  H01L21/8238 ,  H01L29/51 ,  H01L27/092 ,  H01L27/02 ,  H01L27/04 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/423

Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a low voltage transistor device is disposed in a low voltage region defined on a substrate. The low voltage transistor device comprises a low voltage gate electrode and a first gate dielectric separating the low voltage gate electrode from the substrate. A high voltage transistor device is disposed in a high voltage region defined on the substrate. The high voltage transistor device comprises a high voltage gate electrode and a high voltage gate dielectric separating the high voltage gate electrode from the substrate. A first interlayer dielectric layer is disposed over the substrate surrounding the low voltage transistor device and the high voltage transistor device. The high voltage gate electrode is disposed on the first interlayer dielectric layer and separated from the substrate by the first interlayer dielectric layer.

公开(公告)号：US20200035672A1

公开(公告)日：2020-01-30

申请号：US16578299

申请日：2019-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kong-Beng Thei ,  Dun-Nian Yaung ,  Fu-Jier Fan ,  Hsing-Chih Lin ,  Hsiao-Chin Tuan ,  Jen-Cheng Liu ,  Alexander Kalnitsky ,  Yi-Sheng Chen

IPC: H01L27/06 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L23/522 ,  H01L23/48

Abstract: A three-dimensional (3D) integrated circuit (IC) and associated forming method are provided. In some embodiments, a second IC die is bonded to a first IC die through a second bonding structure and a first bonding structure at a bonding interface. The bonding encloses a seal-ring structure in a peripheral region of the 3D IC in the first and second IC dies. The seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate. The bonding forms a plurality of through silicon via (TSV) coupling structures at the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure by electrically and correspondingly connects a first plurality of TSV wiring layers and inter-wire vias and a second plurality of TSV wiring layers and inter-wire vias.

公开(公告)号：US20190081041A1

公开(公告)日：2019-03-14

申请号：US16101843

申请日：2018-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kong-Beng Thei ,  Chien-Chih Chou ,  Fu-Jier Fan ,  Hsiao-Chin Tuan ,  Yi-Huan Chen ,  Alexander Kalnitsky ,  Yi-Sheng Chen

IPC: H01L27/088 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/02 ,  H01L27/04 ,  H01L29/51

CPC classification number: H01L27/088 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/02 ,  H01L27/0203 ,  H01L27/04 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/42364 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a first transistor gate stack is disposed in a low voltage region defined on a substrate. The first transistor gate stack comprises a first gate electrode and a first gate dielectric separating the first gate electrode from the substrate. A third transistor gate stack is disposed in a high voltage region defined on the substrate. The third transistor gate stack comprises a third gate electrode and a third gate dielectric separating the third gate electrode from the substrate. The third gate dielectric comprises an oxide component and a first interlayer dielectric layer.

公开(公告)号：US20210273119A1

公开(公告)日：2021-09-02

申请号：US17324402

申请日：2021-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Liang-Yu Su ,  Chih-Wen Yao ,  Hsiao-Chin Tuan ,  Ming-Ta Lei

IPC: H01L29/93 ,  H01L27/08 ,  H01L29/66 ,  H01L29/06

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a varactor comprising a reduced surface field (RESURF) region. The method includes forming a drift region having a first doping type within a substrate. A RESURF region having a second doping type is formed within the substrate such that the RESURF region is below the drift region. A gate structure is formed on the substrate. A pair of contact regions is formed within the substrate on opposing sides of the gate structure. The contact regions respectively abut the drift region and have the first doping type, and wherein the first doping type is opposite the second doping type.

公开(公告)号：US10964692B2

公开(公告)日：2021-03-30

申请号：US16578299

申请日：2019-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kong-Beng Thei ,  Dun-Nian Yaung ,  Fu-Jier Fan ,  Hsing-Chih Lin ,  Hsiao-Chin Tuan ,  Jen-Cheng Liu ,  Alexander Kalnitsky ,  Yi-Sheng Chen

IPC: H01L21/00 ,  H01L27/06 ,  H01L23/48 ,  H01L23/00 ,  H01L23/522 ,  H01L23/31 ,  H01L21/48

Abstract: A three-dimensional (3D) integrated circuit (IC) and associated forming method are provided. In some embodiments, a second IC die is bonded to a first IC die through a second bonding structure and a first bonding structure at a bonding interface. The bonding encloses a seal-ring structure in a peripheral region of the 3D IC in the first and second IC dies. The seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate. The bonding forms a plurality of through silicon via (TSV) coupling structures at the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure by electrically and correspondingly connects a first plurality of TSV wiring layers and inter-wire vias and a second plurality of TSV wiring layers and inter-wire vias.

公开(公告)号：US20200091310A1

公开(公告)日：2020-03-19

申请号：US16693670

申请日：2019-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kong-Beng Thei ,  Chien-Chih Chou ,  Hsiao-Chin Tuan ,  Yi-Huan Chen ,  Alexander Kalnitsky

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/78

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.

公开(公告)号：US20190393322A1

公开(公告)日：2019-12-26

申请号：US16562953

申请日：2019-09-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kong-Beng Thei ,  Chien-Chih Chou ,  Hsiao-Chin Tuan ,  Yi-Huan Chen ,  Alexander Kalnitsky

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/78

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.