公开(公告)号：US12033919B2

公开(公告)日：2024-07-09

申请号：US17144717

申请日：2021-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zheng-Xun Li ,  Min-Feng Kao ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Dun-Nian Yaung

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76898

Abstract: Some embodiments relate to a semiconductor structure including a semiconductor substrate, and n interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a dielectric structure and a plurality of metal lines that are stacked over one another in the dielectric structure. A through substrate via (TSV) extends through the semiconductor substrate to contact a metal line of the plurality of metal lines. A protective sleeve is disposed along outer sidewalls of the TSV and separates the outer sidewalls of the TSV from the dielectric structure of the interconnect structure.

公开(公告)号：US11862535B2

公开(公告)日：2024-01-02

申请号：US17177660

申请日：2021-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Ling Shih ,  Wei Chuang Wu ,  Shih Kuang Yang ,  Hsing-Chih Lin ,  Jen-Cheng Liu

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/308 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/308 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/5226

Abstract: The present disclosure relates an integrated chip. The integrated chip includes a semiconductor device arranged along a first side of a semiconductor substrate. The semiconductor substrate has one or more sidewalls extending from the first side of the semiconductor substrate to an opposing second side of the semiconductor substrate. A dielectric liner lines the one or more sidewalls of the semiconductor substrate. A through-substrate-via (TSV) is arranged between the one or more sidewalls and is separated from the semiconductor substrate by the dielectric liner. The TSV has a first width at a first distance from the second side and a second width at a second distance from the second side. The first width is smaller than the second width and the first distance is smaller than the second distance.

公开(公告)号：US20230411277A1

公开(公告)日：2023-12-21

申请号：US17842972

申请日：2022-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Hsien Lin ,  Hsing-Chih Lin ,  Ke Chun Liu ,  Min-Feng Kao ,  Kuan-Hua Lin

IPC: H01L23/522 ,  G06F30/392 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L23/5226 ,  G06F30/392 ,  H01L28/91

Abstract: Capacitors and interconnect structures that couple transistors to one another include parallel stacked metal lines separated by dielectric layers. When capacitors and interconnect structures are combined, each top metal capacitor plate can be coupled to the nearest upper metal line by a through-via, while each bottom metal capacitor plate can be coupled directly to the nearest lower metal line without a via. When a back end of line (BEOL) cell includes multiple capacitors, and design rules require shrinking the cell dimensions, substituting an alternative design that has fewer through-vias can facilitate compaction of the BEOL cell. Similarly, placing capacitors in close proximity so that they can share through-vias can allow even further compaction.

公开(公告)号：US20200312817A1

公开(公告)日：2020-10-01

申请号：US16902539

申请日：2020-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao ,  Yung-Lung Lin ,  Shih-Han Huang ,  I-Nan Chen

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/48 ,  H01L25/00 ,  H01L23/00 ,  H01L23/532

Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. A third IC die is bonded to the second IC die by a second bonding structure. The second bonding structure is arranged between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. The second bonding structure further comprises conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.

公开(公告)号：US10727205B2

公开(公告)日：2020-07-28

申请号：US15998455

申请日：2018-08-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao ,  Yung-Lung Lin ,  Shih-Han Huang ,  I-Nan Chen

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/48 ,  H01L23/532 ,  H01L25/00 ,  H01L23/00

Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. The first bonding structure contacts a first interconnect structure of the first IC die and a second interconnection structure of the second IC die, and has a first portion and a second portion hybrid bonded together. A third IC die is bonded to the second IC die by a third bonding structure. The third bonding structure comprises a second TSV (through substrate via) disposed through the second substrate of the second IC die and includes varies bonding structures according to varies embodiments of the invention.

公开(公告)号：US20200027790A1

公开(公告)日：2020-01-23

申请号：US16584824

申请日：2019-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Han Huang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao

IPC: H01L21/822 ,  H01F17/00 ,  H01F41/04 ,  H01L21/768 ,  H01L23/00 ,  H01L27/08 ,  H01L49/02 ,  H01L23/522 ,  H01L25/065 ,  H01L27/06

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first conductive wire within a first dielectric structure formed on a first surface of a first substrate. A through-substrate-via (TSV) is formed to extend though the first substrate. A second conductive wire is formed within a second dielectric structure formed on a second surface of the first substrate opposing the first surface. The TSV electrically couples the first conductive wire and the second conductive wire. The first conductive wire, the second conductive wire, and the TSV define an inductor that wraps around an axis.

公开(公告)号：US10510592B2

公开(公告)日：2019-12-17

申请号：US15218488

申请日：2016-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Kuan-Chieh Huang

IPC: H01L21/768 ,  H01L27/088 ,  H01L23/48 ,  H01L23/522 ,  H01L21/762 ,  H01L21/822 ,  H01L27/06 ,  H01L23/525

Abstract: An integrated circuit (IC) provides high performance and high functional density. A first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure are respectively under and over a semiconductor substrate. A first electronic device and a second electronic device are between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure. A through substrate via (TSV) extends through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure. A method for manufacturing the IC is also provided.

公开(公告)号：US09876086B2

公开(公告)日：2018-01-23

申请号：US14105341

申请日：2013-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Hsing-Chih Lin

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11521

CPC classification number: H01L29/42324 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

Abstract: Embodiments of mechanisms for forming a memory device structure are provided. The memory device includes a first gate stack structure. The first gate stack structure includes a first dielectric layer over a semiconductor substrate. The first gate stack structure also includes a first floating gate over the first dielectric layer, and the first floating gate has a tip corner. The first gate stack structure further includes a second dielectric layer conformally covering an upper surface and sidewalls of the first floating gate. The second dielectric layer has a substantially uniform thickness. In addition, the first gate stack structure includes a first control gate over the second dielectric layer and partially over the first floating gate.

公开(公告)号：US09263437B2

公开(公告)日：2016-02-16

申请号：US14133037

申请日：2013-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh-Shuo Liang ,  Hsing-Chih Lin ,  Yu-Lung Yeh ,  Chih-Ho Tai ,  Ching-Hung Huang

IPC: H01L29/78 ,  H01L27/06 ,  H01L23/522 ,  H01L49/02 ,  H01L23/532

CPC classification number: H01L27/0688 ,  H01L23/5223 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of mechanisms for forming a metal-insulator-metal (MIM) capacitor structure are provided. The metal-insulator-metal capacitor structure includes a substrate. The MIM capacitor structure also includes a CBM layer formed on the substrate, and the CBM layer includes a bottom barrier layer, a main metal layer and a top barrier layer. The MIM capacitor structure further includes a first high-k dielectric layer formed on the CBM layer, an insulating layer formed on the first high-k dielectric layer and a second high-k dielectric layer formed on the insulating layer. The MIM capacitor structure also includes a CTM layer formed on the second high-k dielectric layer, and the CBM layer includes a bottom barrier layer, a main metal layer and a top barrier layer.

Abstract translation: 提供了用于形成金属 - 绝缘体 - 金属（MIM）电容器结构的机构的实施例。 金属 - 绝缘体 - 金属电容器结构包括基板。 MIM电容器结构还包括在衬底上形成的CBM层，并且CBM层包括底部阻挡层，主金属层和顶部阻挡层。 MIM电容器结构还包括形成在CBM层上的第一高k电介质层，形成在第一高k电介质层上的绝缘层和形成在绝缘层上的第二高k电介质层。 MIM电容器结构还包括形成在第二高k电介质层上的CTM层，并且CBM层包括底部阻挡层，主金属层和顶部阻挡层。

公开(公告)号：US11996429B2

公开(公告)日：2024-05-28

申请号：US17525926

申请日：2021-11-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Nan Tu ,  Yu-Lung Yeh ,  Hsing-Chih Lin ,  Chien-Chang Huang ,  Shih-Shiung Chen

IPC: H01L27/146

CPC classification number: H01L27/14625 ,  H01L27/14621 ,  H01L27/14645 ,  H01L27/14683 ,  H01L27/14685 ,  H01L27/14689

Abstract: A semiconductor device includes a device layer, a semiconductor layer, a sensor element, a dielectric layer, a color filter layer, and a micro-lens. The semiconductor layer is over the device layer. The semiconductor layer has a plurality of microstructures thereon. Each of the microstructures has a substantially triangular cross-section. The sensor element is under the microstructures of the semiconductor layer and is configured to sense incident light. The dielectric layer is over the microstructures of the semiconductor layer. The color filter layer is over the dielectric layer. The micro-lens is over the color filter layer.