公开(公告)号：US20210384034A1

公开(公告)日：2021-12-09

申请号：US17401845

申请日：2021-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Li-Min Chen ,  Neng-Jye Yang ,  Ming-Hsi Yeh ,  Shun Wu Lin ,  Kuo-Bin Huang

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L29/267

Abstract: An etchant is utilized to remove a semiconductor material. In some embodiments an oxidizer is added to the etchant in order to react with surrounding semiconductor material and form a protective layer. The protective layer is utilized to help prevent damage that could occur from the other components within the etchant.

公开(公告)号：US20210366704A1

公开(公告)日：2021-11-25

申请号：US17391537

申请日：2021-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Yao-Wen Hsu ,  Neng-Jye Yang ,  Li-Min Chen ,  Chia-Wei Wu ,  Kuan-Lin Chen ,  Kuo Bin Huang

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  G03F7/32 ,  G03F7/20 ,  G03F7/09 ,  H01L21/033

Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.

公开(公告)号：US20240194522A1

公开(公告)日：2024-06-13

申请号：US18586925

申请日：2024-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Kuo-Bin Huang ,  Neng-Jye Yang ,  Li-Min Chen

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/306 ,  H01L21/48 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76823 ,  H01L21/02307 ,  H01L21/30604 ,  H01L21/4857 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5329

Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.

公开(公告)号：US11855193B2

公开(公告)日：2023-12-26

申请号：US17648166

申请日：2022-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Chun-Neng Lin ,  Ming-Hsi Yeh ,  Chieh-Wei Chen ,  Tzu-Ang Chiang

IPC: H01L29/66 ,  H01L21/84 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/845 ,  H01L29/7854

Abstract: A semiconductor device includes a gate electrode over a channel region of a semiconductor fin, first spacers over the semiconductor fin, and second spacers over the semiconductor fin. A lower portion of the gate electrode is between the first spacers. An upper portion of the gate electrode is above the first spacers. The second spacers are adjacent the first spacers opposite the gate electrode. The upper portion of the gate electrode is between the second spacers.

公开(公告)号：US20230207384A1

公开(公告)日：2023-06-29

申请号：US18178948

申请日：2023-03-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Kuo-Bin Huang ,  Neng-Jye Yang ,  Li-Min Chen

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/48 ,  H01L21/306

CPC classification number: H01L21/76823 ,  H01L21/02307 ,  H01L21/4857 ,  H01L21/30604 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.

公开(公告)号：US20200105587A1

公开(公告)日：2020-04-02

申请号：US16145457

申请日：2018-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Kuo-Bin Huang ,  Neng-Jye Yang ,  Li-Min Chen

IPC: H01L21/768 ,  H01L21/306 ,  H01L21/48 ,  H01L21/02

Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.

公开(公告)号：US11990339B2

公开(公告)日：2024-05-21

申请号：US17391537

申请日：2021-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Yao-Wen Hsu ,  Neng-Jye Yang ,  Li-Min Chen ,  Chia-Wei Wu ,  Kuan-Lin Chen ,  Kuo Bin Huang

IPC: H01L21/027 ,  G03F7/09 ,  G03F7/20 ,  G03F7/32 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  G03F7/095 ,  H01L21/306

CPC classification number: H01L21/0273 ,  G03F7/094 ,  G03F7/20 ,  G03F7/32 ,  H01L21/0228 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31111 ,  G03F7/095 ,  H01L21/30608

Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.

公开(公告)号：US11978801B2

公开(公告)日：2024-05-07

申请号：US17814865

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Chun-Neng Lin ,  Chieh-Wei Chen ,  Tzu-Ang Chiang ,  Ming-Hsi Yeh

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of forming a semiconductor device includes surrounding a dummy gate disposed over a fin with a dielectric material; forming a gate trench in the dielectric material by removing the dummy gate and by removing upper portions of a first gate spacer disposed along sidewalls of the dummy gate, the gate trench comprising a lower trench between remaining lower portions of the first gate spacer and comprising an upper trench above the lower trench; forming a gate dielectric layer, a work function layer and a glue layer successively in the gate trench; removing the glue layer and the work function layer from the upper trench; filling the gate trench with a gate electrode material after the removing; and removing the gate electrode material from the upper trench, remaining portions of the gate electrode material forming a gate electrode.

公开(公告)号：US20240063060A1

公开(公告)日：2024-02-22

申请号：US18501653

申请日：2023-11-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh-Wei Chen ,  Jian-Jou Lian ,  Tzu-Ang Chiang ,  Chun-Neng Lin ,  Ming-Hsi Yeh

IPC: H01L21/8234 ,  G03F1/46 ,  G03F7/09 ,  H01L21/027 ,  H01L29/66

CPC classification number: H01L21/823431 ,  G03F1/46 ,  G03F7/091 ,  H01L21/0276 ,  H01L21/82345 ,  H01L29/66795

Abstract: A method includes depositing a first work function layer over a gate dielectric layer, forming a first hard mask layer over the first work function layer, forming a photoresist mask over the first hard mask layer, where forming the photoresist mask includes depositing a bottom anti-reflective coating (BARC) layer over the first hard mask layer, etching a portion of the BARC layer, etching a portion of the first hard mask layer using the BARC layer as a mask, etching a portion of the first work function layer to expose a portion of the gate dielectric layer through the first hard mask layer and the first work function layer, removing the first hard mask layer, and depositing a second work function layer over the first work function layer and over the portion of the gate dielectric layer.

公开(公告)号：US11848239B2

公开(公告)日：2023-12-19

申请号：US16925918

申请日：2020-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh-Wei Chen ,  Jian-Jou Lian ,  Tzu-Ang Chiang ,  Chun-Neng Lin ,  Ming-Hsi Yeh

IPC: H01L21/8234 ,  H01L21/027 ,  H01L21/336 ,  G03F1/46 ,  G03F7/09 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823431 ,  G03F1/46 ,  G03F7/091 ,  H01L21/0276 ,  H01L21/82345 ,  H01L29/66795

Abstract: A method includes depositing a first work function layer over a gate dielectric layer, forming a first hard mask layer over the first work function layer, forming a photoresist mask over the first hard mask layer, where forming the photoresist mask includes depositing a bottom anti-reflective coating (BARC) layer over the first hard mask layer, etching a portion of the BARC layer, etching a portion of the first hard mask layer using the BARC layer as a mask, etching a portion of the first work function layer to expose a portion of the gate dielectric layer through the first hard mask layer and the first work function layer, removing the first hard mask layer, and depositing a second work function layer over the first work function layer and over the portion of the gate dielectric layer.