公开(公告)号：US20210305084A1

公开(公告)日：2021-09-30

申请号：US17150725

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw

IPC: H01L21/764 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate, an S/D feature disposed over the semiconductor fin, and a first dielectric fin and a second dielectric fin disposed over the substrate, where the semiconductor fin is disposed between the first dielectric fin and the second dielectric fin, where a first air gap is enclosed by a first sidewall of the epitaxial S/D feature and the first dielectric fin, and where a second air gap is enclosed by a second sidewall of the epitaxial S/D feature and the second dielectric fin.

公开(公告)号：US20210202713A1

公开(公告)日：2021-07-01

申请号：US17181607

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Hua Pan ,  Je-Wei Hsu ,  Hua Feng Chen ,  Jyun-Ming Lin ,  Chen-Huang Peng ,  Min-Yann Hsieh ,  Java Wu

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/311 ,  H01L29/78 ,  H01L29/45 ,  H01L21/768 ,  H01L29/417 ,  H01L23/485

Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

公开(公告)号：US20210082686A1

公开(公告)日：2021-03-18

申请号：US16573656

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Che Chiang ,  Wei-Chih Kao ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08

Abstract: A method includes providing a semiconductor substrate; epitaxially growing a blocking layer from a top surface of the semiconductor substrate, wherein the blocking layer has a lattice constant different from the semiconductor substrate; epitaxially growing a semiconductor layer above the blocking layer; patterning the semiconductor layer to form a semiconductor fin, wherein the blocking layer is under the semiconductor fin; forming a source/drain (S/D) feature in contact with the semiconductor fin; and forming a gate structure engaging the semiconductor fin.

公开(公告)号：US10074558B1

公开(公告)日：2018-09-11

申请号：US15800359

申请日：2017-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Che Tsai ,  Min-Yann Hsieh ,  Hua-Feng Chen ,  Kuo-Hua Pan

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/8234 ,  H01L21/285 ,  H01L21/311 ,  H01L23/528

CPC classification number: H01L21/7682 ,  H01L21/28568 ,  H01L21/31116 ,  H01L21/764 ,  H01L21/76843 ,  H01L21/76882 ,  H01L21/76883 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53295

Abstract: The present disclosure provides a method that includes forming an isolation feature in a semiconductor substrate; forming a first fin and a second fin on the semiconductor substrate, wherein the first and second fins are laterally separated by the isolation feature; and forming an elongated contact feature landing on the first and second fins. The elongated contact feature is further embedded in the isolation feature, enclosing an air gap vertically between the contact feature and the isolation feature.

公开(公告)号：US20180082908A1

公开(公告)日：2018-03-22

申请号：US15268890

申请日：2016-09-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Yang Yeh ,  Shun-Jang Liao ,  Shu-Hui Wang ,  Chun-Sheng Liang ,  Kuo-Hua Pan ,  Jeng-Ya David Yeh

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/4966

Abstract: A semiconductor device includes a first semiconductor channel, a second semiconductor channel, a first gate stack and a second gate stack. The first gate stack includes N-work function metal present on the first semiconductor channel. The second gate stack includes N-work function metal present on the second semiconductor channel. The N-work function metal in the first gate stack and the second gate stack are substantially different. The difference includes at least one of N-work function metal type and N-work function metal amount.

公开(公告)号：US09882023B2

公开(公告)日：2018-01-30

申请号：US15056454

申请日：2016-02-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyun-Ming Lin ,  Hua Feng Chen ,  Kuo-Hua Pan ,  Min-Yann Hsieh ,  C. H. Wu

IPC: H01L21/28 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L23/535

CPC classification number: H01L29/66553 ,  H01L21/28008 ,  H01L21/31111 ,  H01L21/823431 ,  H01L21/823468 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/4238 ,  H01L29/512 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/78

Abstract: A semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a first gate electrode of a transistor, a first sidewall spacer along a sidewall of the gate pattern, a first insulating layer in contact with the first sidewall spacer and having a planarized top surface, and a second sidewall spacer formed on the planarized top surface of the first insulating layer. The second sidewall spacer may be formed over the first sidewall spacer. A width of the second sidewall spacer is equal to or greater than a width of the first sidewall spacer.

公开(公告)号：US12051695B2

公开(公告)日：2024-07-30

申请号：US18360166

申请日：2023-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Shien-Yang Wu

IPC: H01L21/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823462 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a substrate having a first region and a second region. Multiple nanostructures are vertically stacked above the first region of the substrate. A first gate dielectric layer wraps each of the nanostructures. A first gate electrode layer is disposed on the first gate dielectric layer. A fin protruding from the second region of the substrate. The fin includes alternating first and second semiconductor layers with different material compositions. A second gate dielectric layer is disposed on top and sidewall surfaces of the fin. A second gate electrode layer is disposed on the second gate dielectric layer. A thickness of the first gate dielectric layer is smaller than a thickness of the second gate dielectric layer.

公开(公告)号：US11923194B2

公开(公告)日：2024-03-05

申请号：US17728369

申请日：2022-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Che Chiang ,  Wei-Chih Kao ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L21/0245 ,  H01L21/02507 ,  H01L21/02587 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a semiconductor substrate having a first lattice constant, a dopant blocking layer disposed over the semiconductor substrate, the dopant blocking layer having a second lattice constant different from the first lattice constant, and a buffer layer disposed over the dopant blocking layer, the buffer layer having a third lattice constant different from the second lattice constant. The semiconductor device also includes a plurality of channel members suspended over the buffer layer, an epitaxial feature abutting the channel members, and a gate structure wrapping each of the channel members.

公开(公告)号：US20230361124A1

公开(公告)日：2023-11-09

申请号：US18355143

申请日：2023-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuan-Lin Yeh ,  Chun-Jun Lin ,  Kuo-Hua Pan ,  Mu-Chi Chiang

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/768 ,  H10B10/00

CPC classification number: H01L27/0924 ,  H01L29/7851 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66553 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823842 ,  H01L21/762 ,  H01L21/76831 ,  H01L29/66795 ,  H10B10/12

Abstract: A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.

公开(公告)号：US11804402B2

公开(公告)日：2023-10-31

申请号：US17136385

申请日：2020-12-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Che Tsai ,  Min-Yann Hsieh ,  Hua Feng Chen ,  Kuo-Hua Pan

IPC: H01L21/76 ,  H01L29/49 ,  H01L29/76 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/532 ,  H01L21/285 ,  H01L21/311 ,  H01L23/528 ,  H01L23/485 ,  H01L21/764 ,  H01L29/417

CPC classification number: H01L21/7682 ,  H01L21/28568 ,  H01L21/31116 ,  H01L21/764 ,  H01L21/76843 ,  H01L21/76882 ,  H01L21/76883 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53295 ,  H01L29/41791

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.