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公开(公告)号：US12013570B2
公开(公告)日：2024-06-18
申请号：US18094839
申请日：2023-01-09
发明人： Tao-Cheng Liu , Tsai-Hao Hung , Shih-Chi Kuo
IPC分类号： G02B6/136 , G02B5/18 , G02B6/122 , H01L21/306 , H01L21/308
CPC分类号： G02B6/136 , G02B5/1819 , G02B5/1857 , G02B6/1225 , H01L21/30608 , H01L21/3086
摘要： A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
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公开(公告)号：US10962424B2
公开(公告)日：2021-03-30
申请号：US16408769
申请日：2019-05-10
发明人： Tsai-Hao Hung , Shih-Chi Kuo
摘要： The structure of a micro-electro-mechanical system (MEMS) thermal sensor and a method of fabricating the MEMS thermal sensor are disclosed. A method of fabricating a MEMS thermal sensor includes forming first and second sensing electrodes with first and second electrode fingers, respectively, on a substrate and forming a patterned layer with a rectangular cross-section between a pair of the first electrode fingers. The first and second electrode fingers are formed in an interdigitated configuration and suspended above the substrate. The method further includes modifying the patterned layer to have a curved cross-section between the pair of the first electrode fingers, forming a curved sensing element on the modified patterned layer to couple to the pair of the first electrode fingers, and removing the modified patterned layer.
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13.发明授权公开(公告)号：US10950485B2
公开(公告)日：2021-03-16
申请号：US16559089
申请日：2019-09-03
发明人： Tsai-Hao Hung , Ping-Cheng Ko , Tzu-Yang Lin , Fang-Yu Liu , Cheng-Han Wu
IPC分类号： H01L21/687 , H01L21/677 , H01L21/67 , H05F1/00 , H01L21/66
摘要： Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.
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公开(公告)号：US20200003550A1
公开(公告)日：2020-01-02
申请号：US16407799
申请日：2019-05-09
发明人： Shih-Yu LIAO , Shih-Chi Kuo , Tsai-Hao Hung , Tsung-Hsien Lee
摘要： The present disclosure is directed to a method and system for monitoring a distance between a shutter and a reference point in a processing module. For example, the method includes moving a shutter relative to a substrate support in a wafer processing module and determining a distance between the shutter and a wall of the wafer processing module with a measurement device. In response to the distance being greater than a value, the method further includes transferring a substrate to the substrate support, and in response to the distance being equal to or less than the value, the method includes resetting the shutter.
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公开(公告)号：US10274678B1
公开(公告)日：2019-04-30
申请号：US15936042
申请日：2018-03-26
发明人： Tao-Cheng Liu , Tsai-Hao Hung , Shih-Chi Kuo
IPC分类号： G02B6/136 , G02B6/122 , H01L21/308 , H01L21/306
摘要： A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
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16.发明授权公开(公告)号：US11854860B2
公开(公告)日：2023-12-26
申请号：US18055784
申请日：2022-11-15
发明人： Tsai-Hao Hung , Ping-Cheng Ko , Tzu-Yang Lin , Fang-Yu Liu , Cheng-Han Wu
IPC分类号： H01L21/687 , H01L21/67 , H01L21/677 , H01L21/66 , H05F1/00
CPC分类号： H01L21/68757 , H01L21/6719 , H01L21/67167 , H01L21/67173 , H01L21/67196 , H01L21/67201 , H01L21/67242 , H01L21/67742 , H01L22/10 , H05F1/00
摘要： Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.
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公开(公告)号：US11585982B2
公开(公告)日：2023-02-21
申请号：US17182151
申请日：2021-02-22
发明人： Tao-Cheng Liu , Tsai-Hao Hung , Shih-Chi Kuo
IPC分类号： G02B6/136 , G02B6/122 , H01L21/308 , H01L21/306 , G02B5/18
摘要： A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
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公开(公告)号：US11309347B2
公开(公告)日：2022-04-19
申请号：US16788145
申请日：2020-02-11
发明人： Chun-Wei Hsu , Tsai-Hao Hung , Chung-Yu Lin , Ying-Hsun Chen
IPC分类号： H01L27/146 , H01L31/18 , H01L31/028 , H01L31/0236 , H01L31/0232 , H01L31/0304 , H01L31/032 , H01L31/0296
摘要： An integrated circuit includes a photodetector. The photodetector includes one or more dielectric structures positioned in a trench in a semiconductor substrate. The photodetector includes a photosensitive material positioned in the trench and covering the one or more dielectric structures. A dielectric layer covers the photosensitive material. The photosensitive material has an index of refraction that is greater than the indices of refraction of the dielectric structures and the dielectric layer.
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公开(公告)号：US11227958B2
公开(公告)日：2022-01-18
申请号：US16863989
申请日：2020-04-30
发明人： Tao-Cheng Liu , Tsai-Hao Hung , Ying-Hsun Chen
IPC分类号： H01L31/18 , H01L31/0232 , H01L31/0352 , H01L31/054 , H01L31/02 , H01L31/04
摘要： An integrated circuit includes a photodetector. The photodetector includes a circular optical grating formed in an annular trench in a semiconductor substrate. The circular optical grating includes dielectric fins and photosensitive fins positioned in the annular trench. The circular optical grating is configured to receive incident light and to direct the incident light around the annular trench through the dielectric fins and the photosensitive fins until the light is absorbed by one of the photosensitive fins.
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公开(公告)号：US20210280636A1
公开(公告)日：2021-09-09
申请号：US17330295
申请日：2021-05-25
发明人： Chun-Chieh MO , Shih-Chi Kuo , Tsai-Hao Hung
摘要： A memory includes: a dielectric fin formed over a substrate; and a pair of memory cells disposed along respective sidewalls of the dielectric fin, each of the pair of memory cells comprising: a first conductor layer; a selector layer; a resistive material layer; and a second conductor layer, wherein the first conductor layer, selector layer, resistive material layer, and second conductor layer each includes upper and lower boundaries, and at least one of the upper and lower boundaries is tilted away from one of the sidewalls of the dielectric fin by an angle.
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