公开(公告)号：US07615459B1

公开(公告)日：2009-11-10

申请号：US12190398

申请日：2008-08-12

申请人： Yushi Inoue ,  Tetsuya Ohnishi ,  Kazuya Ishihara ,  Takahiro Shibiuya ,  Yasunari Hosoi ,  Shinobu Yamazaki ,  Takashi Nakano

发明人： Yushi Inoue ,  Tetsuya Ohnishi ,  Kazuya Ishihara ,  Takahiro Shibiuya ,  Yasunari Hosoi ,  Shinobu Yamazaki ,  Takashi Nakano

IPC分类号： H01L21/20

CPC分类号： H01L45/04 ,  H01L45/1226 ,  H01L45/124 ,  H01L45/146 ,  H01L45/1633

摘要： A manufacturing method for a variable resistive element according to which a stable switching operation can be achieved with excellent reproducibility is provided. A conductive thin film is deposited on a semiconductor substrate and patterned to a predetermined form, and after that, a first interlayer insulating film is deposited. An opening is then created in a predetermined location on the first interlayer insulating film in such a manner that the upper surface of the conductive thin film is exposed and the thickness of the conductive thin film formed at the bottom of this opening is reduced through processing, and after that, an oxidation process is carried out on the periphery of the exposed conductive thin film. As a result, a variable resistor film is formed in the peripheral region of the opening, and this variable resistor film divides the conductive thin film into a first electrode and a second electrode.

摘要翻译： 提供了一种可变电阻元件的制造方法，其中可以以优异的再现性实现稳定的开关操作。 将导电薄膜沉积在半导体衬底上并图案化为预定形式，之后沉积第一层间绝缘膜。 然后在第一层间绝缘膜上的预定位置处以导电薄膜的上表面露出并且形成在该开口底部的导电薄膜的厚度通过加工而减小的方式形成开口， 之后，在露出的导电性薄膜的周围进行氧化处理。 结果，在开口的周边区域中形成可变电阻膜，该可变电阻膜将导电薄膜分成第一电极和第二电极。

公开(公告)号：US5940734A

公开(公告)日：1999-08-17

申请号：US982832

申请日：1997-12-02

申请人： Yushi Inoue

发明人： Yushi Inoue

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/31055 ,  H01L21/76819

摘要： An insulating film 16, made of BPSG, etc., is formed on a substrate 10 by CVD, covering an uneven surface, and then is subjected to thermal treatment to fluidize the film and to reduce the step. Hydrogen silsesquioxane resin solution is coated on the film 16 by spin coating, subjected to the first annealing at a relatively low temperature, and then to the second annealing at relatively high temperature, to form a glass film 18. The lamination of the films 16 and 18 is etched back under the dry etching conditions where the etch rates of the films 16 and 18 become approximately equal, until film 18 is completely removed, to planarize the film 16. A wiring is formed on the planarized surface. The surface of the insulating film serving as an underlying layer of a wiring can be planarized uniformly and with good reproducibility.

摘要翻译： 通过CVD在基板10上形成由BPSG等制成的绝缘膜16，覆盖不平坦表面，然后进行热处理以使膜流态化并降低步骤。 通过旋涂将氢倍半硅氧烷树脂溶液涂布在膜16上，在比较低的温度下进行第一退火，然后进行相对高温的第二次退火，形成玻璃膜18.膜16和 18在干蚀刻条件下被回蚀刻，其中膜16和18的蚀刻速率变得大致相等，直到膜18被完全去除，以使膜16平坦化。在平坦化表面上形成布线。 作为布线的下层的绝缘膜的表面可以均匀平坦化并具有良好的再现性。

公开(公告)号：US09159664B2

公开(公告)日：2015-10-13

申请号：US13178093

申请日：2011-07-07

申请人： Yushi Inoue ,  Yukitoshi Hirose

发明人： Yushi Inoue ,  Yukitoshi Hirose

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L23/64 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC分类号： H01L23/49838 ,  H01L23/3128 ,  H01L23/64 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor device may include, but is not limited to: a wiring hoard; and first and second chips stacked over the wiring board. The wiring board includes a plurality of first data terminals and a plurality of second data terminals. One of the first and second chips is sandwiched between the wiring board and the other of the first and second chips. The first chip includes a plurality of first data pads. The second chip includes a plurality of second data pads and a plurality of third data pads. The first data terminals of the wiring board are electrically connected respectively to the first data pads of the first chip and further respectively to the second data pads of the second chip. The second data terminals are electrically connected respectively to the third data pads of the second chip and electrically disconnected from the first chip.

摘要翻译： 半导体器件可以包括但不限于：布线板; 以及堆叠在布线板上的第一和第二芯片。 布线板包括多个第一数据终端和多个第二数据终端。 第一和第二芯片中的一个夹在布线板和第一和第二芯片中的另一个之间。 第一芯片包括多个第一数据焊盘。 第二芯片包括多个第二数据焊盘和多个第三数据焊盘。 布线板的第一数据端子分别电连接到第一芯片的第一数据焊盘，并且进一步分别连接到第二芯片的第二数据焊盘。 第二数据端子分别电连接到第二芯片的第三数据焊盘，并与第一芯片电断开。

公开(公告)号：US07402513B2

公开(公告)日：2008-07-22

申请号：US11034616

申请日：2005-01-12

申请人： Takanori Sonoda ,  Kazumasa Mitsumune ,  Kenichiroh Abe ,  Yushi Inoue ,  Tsukasa Doi

发明人： Takanori Sonoda ,  Kazumasa Mitsumune ,  Kenichiroh Abe ,  Yushi Inoue ,  Tsukasa Doi

IPC分类号： H01L21/461 ,  H01L21/4763 ,  H01L21/469

CPC分类号： H01L21/0217 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02318 ,  H01L21/3143 ,  H01L21/31625 ,  H01L21/3185 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837

摘要： It is an object of the present invention to provide a method for forming an interlayer insulation film suppressing the occurrence of voids in the interlayer insulation film.A method for forming an interlayer insulation film of the present invention, comprising the steps of: (1) forming an etching stopper film of a silicon nitride film on an entire surface including a step part on a semiconductor substrate having the step part with an aspect ratio of ≧3; (2) forming an interlayer insulation film of an impurity-doped silicate film on the silicon nitride film; and (3) performing reflow of the interlayer insulation film by a heat treatment, wherein the formation of the silicon nitride film is controlled such that the N—H bond density of the silicon nitride film is 1.0×1022 pieces/cm3 or less.According to the method for forming the interlayer insulation film of the present invention, the occurrence of the voids can be suppressed in the interlayer insulation film even if the aspect ratio of the step part formed on the semiconductor substrate is 3 or more. Also, the damage applied to the semiconductor device by reflow can be reduced.

摘要翻译： 本发明的目的是提供一种形成层间绝缘膜的方法，该层间绝缘膜抑制层间绝缘膜中空隙的发生。 一种形成本发明的层间绝缘膜的方法，包括以下步骤：（1）在具有该步骤部分的半导体衬底上的包括台阶部分的整个表面上形成氮化硅膜的蚀刻阻挡膜，该半导体衬底具有一个方面 比值> = 3; （2）在氮化硅膜上形成杂质掺杂硅酸盐膜的层间绝缘膜; 和（3）通过热处理进行层间绝缘膜的回流，其中控制氮化硅膜的形成，使得氮化硅膜的NH键密度为1.0×10 22个/ cm 3以下。 根据本发明的层间绝缘膜的形成方法，即使形成在半导体基板上的台阶部的纵横比为3以上，也能够抑制层间绝缘膜的空隙的发生。 此外，可以减少通过回流施加到半导体器件的损坏。

公开(公告)号：US20050159015A1

公开(公告)日：2005-07-21

申请号：US11034616

申请日：2005-01-12

申请人： Takanori Sonoda ,  Kazumasa Mitsumune ,  Kenichiroh Abe ,  Yushi Inoue ,  Tsukasa Doi

发明人： Takanori Sonoda ,  Kazumasa Mitsumune ,  Kenichiroh Abe ,  Yushi Inoue ,  Tsukasa Doi

IPC分类号： C23C16/34 ,  H01L21/28 ,  H01L21/31 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/522 ,  H01L21/4763 ,  H01L21/469

CPC分类号： H01L21/0217 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02318 ,  H01L21/3143 ,  H01L21/31625 ,  H01L21/3185 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837

摘要： It is an object of the present invention to provide a method for forming an interlayer insulation film suppressing the occurrence of voids in the interlayer insulation film. A method for forming an interlayer insulation film of the present invention, comprising the steps of: (1) forming an etching stopper film of a silicon nitride film on an entire surface including a step part on a semiconductor substrate having the step part with an aspect ratio of ≧3; (2) forming an interlayer insulation film of an impurity-doped silicate film on the silicon nitride film; and (3) performing reflow of the interlayer insulation film by a heat treatment, wherein the formation of the silicon nitride film is controlled such that the N—H bond density of the silicon nitride film is 1.0×1022 pieces/cm3 or less. According to the method for forming the interlayer insulation film of the present invention, the occurrence of the voids can be suppressed in the interlayer insulation film even if the aspect ratio of the step part formed on the semiconductor substrate is 3 or more. Also, the damage applied to the semiconductor device by reflow can be reduced.

摘要翻译： 本发明的目的是提供一种形成层间绝缘膜的方法，该层间绝缘膜抑制层间绝缘膜中空隙的发生。 一种形成本发明的层间绝缘膜的方法，包括以下步骤：（1）在具有该步骤部分的半导体衬底上的包括台阶部分的整个表面上形成氮化硅膜的蚀刻阻挡膜，该半导体衬底具有一个方面 比值> = 3; （2）在氮化硅膜上形成杂质掺杂硅酸盐膜的层间绝缘膜; 和（3）通过热处理进行层间绝缘膜的回流，其中控制氮化硅膜的形成，使得氮化硅膜的NH键密度为1.0×10 22个/ cm 3以下。 根据本发明的层间绝缘膜的形成方法，即使形成在半导体基板上的台阶部的纵横比为3以上，也能够抑制层间绝缘膜的空隙的发生。 此外，可以减少通过回流施加到半导体器件的损坏。

公开(公告)号：US06841467B2

公开(公告)日：2005-01-11

申请号：US09826833

申请日：2001-04-06

申请人： Yushi Inoue

发明人： Yushi Inoue

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/522 ,  H01L21/4763

CPC分类号： H01L21/76807

摘要： A method for producing a semiconductor device comprises forming an opening by etching process using a resist pattern as a mask in a multi-layered film having a first organic insulating film, a first etching stop film and a second organic insulating film being layered in this order such that the opening penetrates from the first organic insulating film to the second organic insulating film, wherein a second etching stop film is formed between the resist pattern and the second organic insulating film to protect the second organic insulating film from being etched during the formation of the opening.

摘要翻译： 一种半导体器件的制造方法，其特征在于，在具有第一有机绝缘膜，第一蚀刻停止膜和第二有机绝缘膜的多层膜中，使用抗蚀剂图案作为掩模，通过蚀刻工序形成开口， 使得开口从第一有机绝缘膜渗透到第二有机绝缘膜，其中在抗蚀剂图案和第二有机绝缘膜之间形成第二蚀刻停止膜，以在形成第二有机绝缘膜期间保护第二有机绝缘膜不被蚀刻 开幕。

公开(公告)号：US06828604B2

公开(公告)日：2004-12-07

申请号：US10136343

申请日：2002-05-02

申请人： Yushi Inoue

发明人： Yushi Inoue

IPC分类号： H01L2710

CPC分类号： H01Q1/38 ,  H01L24/02 ,  H01L2224/04042 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

摘要： A semiconductor device comprising: a MOS transistor having a gate electrode formed on a semiconductor substrate, a wiring connected to the gate electrode via a first insulating film, an antenna pattern for reducing plasma damage in the form of lines/spaces connected to the wiring, and a second insulating film formed on the wiring and the antenna pattern.

摘要翻译： 一种半导体器件，包括：MOS晶体管，其具有形成在半导体衬底上的栅极电极，经由第一绝缘膜连接到栅电极的布线，用于以与布线连接的线/间隔的形式减小等离子体损伤的天线图案， 以及形成在布线和天线图案上的第二绝缘膜。

公开(公告)号：US08450145B2

公开(公告)日：2013-05-28

申请号：US12939640

申请日：2010-11-04

申请人： Yushi Inoue

发明人： Yushi Inoue

IPC分类号： H01L21/00

CPC分类号： H01L45/04 ,  G11C13/0007 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1633

摘要： A first opening and a second opening are formed at the same time over a first metal wiring and a second metal wiring, respectively which are provided as the same layer on a substrate on which a transistor for selecting a memory cell is formed. Then, a variable resistor and an upper electrode are deposited on a whole surface so as to completely fill the first opening with the upper electrode but not to completely fill the second opening with it. Thereafter, a variable resistive element is formed in the first opening and a via hole to connect to the third metal wiring (bit line), in the second opening, at the same time, by performing back-etching until a surface of the second metal wiring is exposed at a bottom of the second opening.

摘要翻译： 在第一金属布线和第二金属布线上同时形成第一开口和第二开口，第一金属布线和第二金属布线在形成用于选择存储单元的晶体管的基板上设置为同一层。 然后，在整个表面上沉积可变电阻器和上电极，以便用上电极完全填充第一开口，但是不能完全填充第二开口。 此后，通过进行逆蚀刻，在第一开口中形成可变电阻元件和通孔，以在第二开口中同时连接到第三金属布线（位线），直到第二金属的表面 布线暴露在第二开口的底部。

公开(公告)号：US20120025163A1

公开(公告)日：2012-02-02

申请号：US13182696

申请日：2011-07-14

申请人： Junya ONISHI ,  Shinobu Yamazaki ,  Kazuya Ishihara ,  Yushi Inoue ,  Yukio Tamai ,  Nobuyoshi Awaya

发明人： Junya ONISHI ,  Shinobu Yamazaki ,  Kazuya Ishihara ,  Yushi Inoue ,  Yukio Tamai ,  Nobuyoshi Awaya

IPC分类号： H01L45/00

CPC分类号： H01L45/04 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/146

摘要： A variable resistance element that can stably perform a switching operation with a property variation being reduced by suppressing a sharp current that accompanies completion of forming process, and a non-volatile semiconductor memory device including the variable resistance element are realized. The non-volatile semiconductor memory device uses the variable resistance element for storing information in which a resistance changing layer is interposed between a first electrode and a second electrode, and a buffer layer is inserted between the first electrode and the resistance changing layer where a switching interface is formed. The buffer layer and the resistance changing layer include n-type metal oxides, and materials of the buffer layer and the resistance changing layer are selected such that energy at a bottom of a conduction band of the n-type metal oxide configuring the buffer layer is lower than that of the n-type metal oxide configuring the resistance changing layer.

摘要翻译： 通过抑制伴随着成形处理的完成的尖锐电流，可以稳定地进行具有特性变化的开关动作的可变电阻元件，以及包括该可变电阻元件的非易失性半导体存储器件。 非易失性半导体存储器件使用可变电阻元件来存储在第一电极和第二电极之间插入电阻变化层的信息，并且缓冲层插入在第一电极和电阻变化层之间，其中开关 界面形成。 缓冲层和电阻变化层包括n型金属氧化物，并且选择缓冲层和电阻变化层的材料，使得构成缓冲层的n型金属氧化物的导带的底部的能量为 低于构成电阻变化层的n型金属氧化物。

公开(公告)号：US20050118833A1

公开(公告)日：2005-06-02

申请号：US10998782

申请日：2004-11-30

申请人： Kazumasa Mitsumune ,  Tsukasa Doi ,  Yushi Inoue ,  Kenichirou Abe ,  Takanori Sonoda

发明人： Kazumasa Mitsumune ,  Tsukasa Doi ,  Yushi Inoue ,  Kenichirou Abe ,  Takanori Sonoda

IPC分类号： H01L23/522 ,  H01L21/31 ,  H01L21/314 ,  H01L21/318 ,  H01L21/768 ,  H01L21/469

CPC分类号： H01L21/02129 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837

摘要： It is an object of the present invention to provide a method for manufacturing a semiconductor device suppressing the occurrence of voids in an insulating film. A method for manufacturing a semiconductor device according to the present invention comprises the steps of: (1) forming an insulating film 11 composed of a thin silicon nitride film on a semiconductor substrate 1 having at least a necessary element and a recessed part 6 so as to cover the recessed part 6; (2) modifying the surface of the insulating film 11; and (3) forming a BPSG film 15 as an interlayer insulation film on the insulating film. The occurrence of voids in the interlayer insulation film 15 is suppressed by the process for modifying the surface.

摘要翻译： 本发明的目的是提供一种制造半导体器件的方法，该半导体器件抑制绝缘膜中空隙的发生。 根据本发明的制造半导体器件的方法包括以下步骤：（1）在具有至少必需元件的半导体衬底1上形成由氮化硅薄膜构成的绝缘膜11，以及凹入部分6，以便 覆盖凹部6; （2）改性绝缘膜11的表面; 和（3）在绝缘膜上形成作为层间绝缘膜的BPSG膜15。 通过改变表面的方法来抑制层间绝缘膜15中的空隙的发生。