公开(公告)号：US20140160215A1

公开(公告)日：2014-06-12

申请号：US14114148

申请日：2012-05-30

申请人： Naohito Saito ,  Yutaka Yamada ,  Maiko Kitade

发明人： Naohito Saito ,  Yutaka Yamada ,  Maiko Kitade

IPC分类号： C09D11/00 ,  B41J11/00

CPC分类号： C09D11/30 ,  B41J11/002 ,  B41M5/0047 ,  B41M5/0064 ,  B41M7/0081 ,  C09D11/101 ,  C09D11/322

摘要： An active-energy-ray-curable inkjet recording ink composition is provided, in which a polymerizable compound having an active-energy-ray-polymerizable group and a polymerizable compound having at least two active-energy-ray-polymerizable groups are used in amounts of 60 to 95 mass % and 5 to 40 mass % relative to the total amount of the active-energy-ray-polymerizable compound, respectively; the polymerizable compound having an active-energy-ray-polymerizable group includes N-vinyl-2-caprolactam and isobornyl acrylate in amounts of 1 to 15 mass % and 1 to 25 mass % relative to the total amount of the active-energy-ray-polymerizable compound, respectively; and the polymerizable compound having at least two active-energy-ray-polymerizable groups includes a polymerizable compound having a vinyl ether group. Furthermore, a method for forming an image is provided.

摘要翻译： 提供了一种活性能量射线固化喷墨记录油墨组合物，其中具有活性能量射线聚合基团和具有至少两个活性能量 - 可射线聚合基团的可聚合化合物的可聚合化合物的用量 相对于活性能量射线聚合性化合物的总量分别为60〜95质量％和5〜40质量％ 具有活性能量射线聚合性基团的聚合性化合物相对于活性能量射线的总量，含有1〜15质量％和1〜25质量％的N-乙烯基-2-己内酰胺和丙烯酸异冰片酯 可聚合化合物; 并且具有至少两个活性能量射线可聚合基团的可聚合化合物包括具有乙烯基醚基团的可聚合化合物。 此外，提供了一种用于形成图像的方法。

公开(公告)号：US08683249B2

公开(公告)日：2014-03-25

申请号：US13310892

申请日：2011-12-05

申请人： Tatsunori Kanai ,  Yutaka Yamada ,  Hideki Yoshida ,  Masaya Tarui

发明人： Tatsunori Kanai ,  Yutaka Yamada ,  Hideki Yoshida ,  Masaya Tarui

IPC分类号： G06F1/26

CPC分类号： G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

摘要： According to one embodiment, a computer system comprises a first memory that stores a first program, a second memory that stores a second program or data, a processor, a first and a second power control circuits. The first power control circuit causes the first memory to operate at a first power consumption when detecting change of an input signal to the processor, and causes the first memory to operate at a second power consumption smaller than the first power consumption and transmits a temporary halt instruction to the processor when the execution of the first program or the second program by the processor is completed. The second power control circuit causes the second memory to operate at a third power consumption before the processor executes the second program, reads or writes the data. The second memory accepts read and write operations while operating at the third power consumption.

摘要翻译： 根据一个实施例，计算机系统包括存储第一程序的第一存储器，存储第二程序或数据的第二存储器，处理器，第一和第二功率控制电路。 当检测到对处理器的输入信号的变化时，第一功率控制电路使得第一存储器以第一功率消耗操作，并且使得第一存储器以比第一功耗小的第二功耗工作，并且发送暂时停止 当处理器执行第一程序或第二程序完成时，指令到处理器。 第二功率控制电路使得第二存储器在处理器执行第二程序之前以第三功耗操作，读取或写入数据。 第二个存储器在以第三次功耗运行的同时接受读写操作。

公开(公告)号：US08502277B2

公开(公告)日：2013-08-06

申请号：US10570279

申请日：2004-08-27

申请人： Kazuhiko Matsumoto ,  Atsuhiko Kojima ,  Satoru Nagao ,  Masanori Katou ,  Yutaka Yamada ,  Kazuhiro Nagaike ,  Yasuo Ifuku ,  Hiroshi Mitani

发明人： Kazuhiko Matsumoto ,  Atsuhiko Kojima ,  Satoru Nagao ,  Masanori Katou ,  Yutaka Yamada ,  Kazuhiro Nagaike ,  Yasuo Ifuku ,  Hiroshi Mitani

IPC分类号： G01N27/403

CPC分类号： G01N27/4145 ,  B82Y10/00 ,  B82Y30/00 ,  G01N27/4146 ,  H01L29/068 ,  H01L29/42364 ,  H01L29/7613

摘要： A sensor capable of detecting detection targets that are necessary to be detected with high sensitivity is provided.It comprises a field-effect transistor 1A having a substrate 2, a source electrode 4 and a drain electrode 5 provided on said substrate 2, and a channel 6 forming a current path between said source electrode 4 and said drain electrode 5; wherein said field-effect transistor 1A comprises:an interaction-sensing gate 9 for immobilizing thereon a specific substance 10 that is capable of selectively interacting with the detection targets; anda gate 7 applied a voltage thereto so as to detect the interaction by the change of the characteristic of said field-effect transistor 1A.

摘要翻译： 提供能够检测需要以高灵敏度检测的检测目标的传感器。 它包括具有衬底2，设置在所述衬底2上的源电极4和漏电极5的场效应晶体管1A以及形成在所述源电极4和所述漏电极5之间的电流通路的通道6; 其中所述场效应晶体管1A包括：用于固定其上能够选择性地与检测目标相互作用的特定物质10的相互作用感测门9; 并且门7向其施加电压，以便通过所述场效应晶体管1A的特性的变化来检测相互作用。

公开(公告)号：US08374021B2

公开(公告)日：2013-02-12

申请号：US13205737

申请日：2011-08-09

申请人： Tatsunori Kanai ,  Masaya Tarui ,  Yutaka Yamada

发明人： Tatsunori Kanai ,  Masaya Tarui ,  Yutaka Yamada

IPC分类号： G11C11/00

CPC分类号： G06F7/588 ,  H04L9/0866

摘要： According to an aspect of embodiments, there is provided a random number generating circuit including at least one magnetic tunnel junction (MTJ) element and a control circuit. The MTJ element comes into a high resistance state corresponding to a first logical value and also comes into a low resistance state corresponding to a second logical value different from the first logical value. The control circuit supplies the MTJ element with a first current for stochastically reversing the MTJ element from the high resistance state to the low resistance state when the MTJ element is in the high resistance state, and supplies the MTJ element with a second current for stochastically reversing the MTJ element from the low resistance state to the high resistance state when the MTJ element is in the low resistance state.

摘要翻译： 根据实施例的一个方面，提供一种包括至少一个磁隧道结（MTJ）元件和控制电路的随机数产生电路。 MTJ元件对应于第一逻辑值进入高电阻状态，并且也进入与不同于第一逻辑值的第二逻辑值相对应的低电阻状态。 当MTJ元件处于高电阻状态时，控制电路向MTJ元件提供第一电流，用于将MTJ元件从高电阻状态随机反向到低电阻状态，并且向MTJ元件提供用于随机反转的第二电流 当MTJ元件处于低电阻状态时，MTJ元件从低电阻状态到高电阻状态。

公开(公告)号：US20120151119A1

公开(公告)日：2012-06-14

申请号：US13371541

申请日：2012-02-13

申请人： Hideki Yoshida ,  Tatsunori Kanai ,  Masaya Tarui ,  Yutaka Yamada

发明人： Hideki Yoshida ,  Tatsunori Kanai ,  Masaya Tarui ,  Yutaka Yamada

IPC分类号： G06F12/00

CPC分类号： G06F3/061 ,  G06F3/0652 ,  G06F3/0656 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/08 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0868 ,  G06F12/1009 ,  G06F12/12 ,  G06F12/123 ,  G06F2212/283 ,  G06F2212/651 ,  G06F2212/7201 ,  G06F2212/7208 ,  G11C7/1072

摘要： A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a nonvolatile memory 12. The volatile memory 11 is provided with a plurality of clean pages. The nonvolatile memory 12 is provided with a plurality of dirty pages and a page table memory unit 51. The operating system 22 is provided with a virtual memory management unit 23 which includes a page transfer unit 25.

摘要翻译： 实施例的虚拟存储器管理装置嵌入在计算机80中，并具有应用程序21，操作系统22，易失性存储器11和非易失性存储器12.易失性存储器11设置有多个 干净的页面。 非易失性存储器12设置有多个脏页和页表存储单元51.操作系统22设置有包括页传送单元25的虚拟存储器管理单元23。

公开(公告)号：US20110136079A1

公开(公告)日：2011-06-09

申请号：US12952931

申请日：2010-11-23

申请人： Joji OKAZAKI ,  Teruta Maeda ,  Koh-ichi Kuremoto ,  Takanori Eto ,  Masahiro Inoue ,  Yutaka Yamada ,  Masashi Takahashi

发明人： Joji OKAZAKI ,  Teruta Maeda ,  Koh-ichi Kuremoto ,  Takanori Eto ,  Masahiro Inoue ,  Yutaka Yamada ,  Masashi Takahashi

IPC分类号： A61C8/00

CPC分类号： A61C8/0081

摘要： To attract a magnet in a denture to a keeper fixed at an embedded implant fixture with a complete closed magnetic circuit and without care to metal allergy, an abutment 1 for a dental magnetic attachment is made of a titanium or alloy, and has a male screw part 1a at a center part of a bottom surface to be screwed into a female screw part 3a of an implant fixture 3, a keeper attaching hole 1b at an upper surface in which a keeper 2 having a uniform thickness and the same size/area as an attracting surface of a magnet is inserted and bonded/fixed; and an engagement part 1c for a rotary tool at a center in the keeper attaching hole 1b and/or at an outer frame part around the keeper attaching hole for screwing the abutment 1 in the implant fixture 3.

摘要翻译： 为了将义齿中的磁体吸引到固定在嵌入式植入物固定装置上的保持器，其具有完全闭合的磁路并且不需要金属过敏，用于牙科磁性附件的支座1由钛或合金制成，并且具有外螺纹 将要拧入植入物固定件3的阴螺纹部分3a的底面的中心部分的部分1a，在上表面处的保持器附接孔1b，其中具有均匀厚度和相同尺寸/面积的保持器2 磁体的吸引表面插入并粘结/固定; 以及用于在保持器安装孔1b中的旋转工具的接合部分1c和/或围绕保持器附接孔的外框架部分，用于将植入物夹具3中的邻接部1旋拧。

公开(公告)号：US07757263B2

公开(公告)日：2010-07-13

申请号：US11374743

申请日：2006-03-14

申请人： Akihiro Tatsuta ,  Yutaka Yamada ,  Tomonori Shiomi

发明人： Akihiro Tatsuta ,  Yutaka Yamada ,  Tomonori Shiomi

IPC分类号： H04N7/16

CPC分类号： H04N21/6168 ,  H04N7/102 ,  H04N21/42607 ,  H04N21/42676 ,  H04N21/6118

摘要： The device includes a cable interface module having a diplexer that outputs a first signal input from a first connector part connected to a cable television network to a third connector part and outputs a second signal input from a second connector part to a first connector part; a video tuner module having a distributor that branches a first signal input from a fourth connector part having a shape capable of connecting to the cable television network and connected to a third connector part and outputs to a fifth connector part, and inputs the other branched signal into a video tuner; and a communication tuner that selects another channel of the signal output from a fifth connector part.

摘要翻译： 所述装置包括具有双工器的电缆接口模块，所述双工器将从连接到有线电视网络的第一连接器部分输入的第一信号输出到第三连接器部分，并将从第二连接器部分输入的第二信号输出到第一连接器部分; 一个视频调谐器模块，具有一个分配器，该分配器将从具有连接到有线电视网络的形状的第四连接器部分输入的第一信号分支并连接到第三连接器部分并输出到第五连接器部分，并输入另一分支信号 进入视频调谐器; 以及通信调谐器，其选择从第五连接器部分输出的信号的另一信道。

公开(公告)号：US07655569B2

公开(公告)日：2010-02-02

申请号：US12020761

申请日：2008-01-28

申请人： Yuichi Inaba ,  Yutaka Yamada ,  Shigehiro Morikawa

发明人： Yuichi Inaba ,  Yutaka Yamada ,  Shigehiro Morikawa

IPC分类号： H01L21/311

CPC分类号： H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

摘要： The invention prevents a wiring layer in a memory region from being exposed to prevent a change in wire resistance and degradation of reliability. A SiO2 film as an etching stopper film which transmits ultraviolet light is formed on pad electrodes and an interlayer insulation film. Then, the SiO2 film on the pad electrodes is etched selectively and the SiO2 film in an EPROM region is left. A silicon nitride film and a polyimide film are then formed on the SiO2 film and on the pad electrodes where the SiO2 film is removed, as a protection film which does not transmit ultraviolet light. The silicon nitride film and the polyimide film on the pad electrodes and in the EPROM region are then selectively removed by etching. Since the SiO2 film functions as an etching stopper at this time, the interlayer insulation film under the SiO2 film is prevented from being etched and a control gate line metal layer is prevented from being exposed.

摘要翻译： 本发明防止存储区域中的布线层暴露，以防止电线电阻的变化和可靠性的劣化。 在焊盘电极和层间绝缘膜上形成作为透射紫外光的蚀刻停止膜的SiO 2膜。 然后，选择性地蚀刻焊盘电极上的SiO 2膜，并且留下EPROM区域中的SiO 2膜。 然后在SiO 2膜上除去SiO 2膜的焊盘电极上形成氮化硅膜和聚酰亚胺膜作为不透射紫外线的保护膜。 然后通过蚀刻选择性地去除焊盘电极和EPROM区域中的氮化硅膜和聚酰亚胺膜。 由于SiO 2膜此时用作蚀刻阻挡层，因此可以防止SiO 2膜下的层间绝缘膜被蚀刻，防止控制栅线金属层露出。

公开(公告)号：US20090189686A1

公开(公告)日：2009-07-30

申请号：US12361964

申请日：2009-01-29

申请人： Yutaka Yamada ,  Tatsunori Kanai

发明人： Yutaka Yamada ,  Tatsunori Kanai

IPC分类号： G05F1/00

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

摘要： Each of computing units on a semiconductor integrated circuit includes a first signal output unit that outputs a first status signal indicating a state of a input/output control unit with regard to an access to a storage unit, a second signal output unit that outputs a second status signal indicating a state of a process control unit with regard to an access to a processing unit, and a power control unit that control ON and OFF of power of the storage unit and the processing unit based on states of the first status signal and the second status signal.

摘要翻译： 半导体集成电路中的每个计算单元包括：第一信号输出单元，其输出指示关于对存储单元的访问的输入/输出控制单元的状态的第一状态信号;第二信号输出单元，其输出第二信号 指示处理单元的访问状态的状态信号;以及功率控制单元，其基于第一状态信号和第一状态信号的状态来控制存储单元和处理单元的电源的接通和断开 第二状态信号。

公开(公告)号：US20090146273A1

公开(公告)日：2009-06-11

申请号：US11997700

申请日：2006-07-28

申请人： Yutaka Yamada ,  Takeshi Kishida ,  Yoshikazu Tamura ,  Yasuo Sogawa ,  Masanori Hirofuji

发明人： Yutaka Yamada ,  Takeshi Kishida ,  Yoshikazu Tamura ,  Yasuo Sogawa ,  Masanori Hirofuji

IPC分类号： H01L23/495

CPC分类号： H01L24/06 ,  H01L23/50 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06153 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48599 ,  H01L2224/49113 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/3011 ,  H01L2224/78 ,  H01L2924/00

摘要： There is provided a semiconductor device adopting, as a layout of pads connected to an external package on an LSI, a zigzag pad layout in which the pads are arranged shifted alternately, which can avoid occurrences of short-circuiting of wires, an increase in chip size due to avoidance of short-circuiting, propagation of power supply or GND noise due to reduction in IO cell interval, and signal transmission delay difference due to displacement of pad positions.In a semiconductor device wherein plural pads on a semiconductor element which are connected to function terminals on an external package are arranged in two lines along the periphery of the semiconductor element, an arrangement order of the plural pads on the semiconductor element is made different from an arrangement order of the function terminals on the external package.

摘要翻译： 提供了一种半导体器件，其采用连接到LSI上的外部封装的焊盘的布局，其中焊盘布置移位的之字形焊盘布局，这可以避免导线短路的发生，芯片的增加 由于避免短路，由于IO单元间隔的减少而导致的电源传播或GND噪声，以及由于焊盘位置的位移引起的信号传输延迟差异。 在半导体装置中，与外部封装上的功能端子连接的半导体元件上的多个焊盘沿着半导体元件的周边配置成两列，半导体元件上的多个焊盘的排列顺序与 功能端子在外部封装上的布置顺序。