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公开(公告)号：US08017994B2
公开(公告)日：2011-09-13
申请号：US12499220
申请日：2009-07-08
IPC分类号： H01L29/792
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/08 , G11C16/12 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11568
摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.
摘要翻译： 通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行数据写入。 当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值 用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。
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公开(公告)号：US20090310409A1
公开(公告)日：2009-12-17
申请号：US12499220
申请日：2009-07-08
IPC分类号： G11C16/04 , H01L29/792 , G11C16/06
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/08 , G11C16/12 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11568
摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.
摘要翻译： 通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行数据写入。 当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值 用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。
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公开(公告)号：US20070230251A1
公开(公告)日：2007-10-04
申请号：US11550335
申请日：2006-10-17
IPC分类号： G11C16/10
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/08 , G11C16/12 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11568
摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.
摘要翻译： 通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行数据写入。 当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值 用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。
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14.发明授权Boosting circuit configured with plurality of boosting circuit units in series 失效升压电路配置有多个串联的升压电路单元公开(公告)号：US06838928B2
公开(公告)日：2005-01-04
申请号：US10339327
申请日：2003-01-10
申请人： Masaaki Mihara
发明人： Masaaki Mihara
CPC分类号： H02M3/073
摘要： By supplying a clock signal from an OSC to four stages of boosting circuit units connected in series, the boosting circuit units are rendered active. A delay element is inserted in the line of the clock signal to prevent all the boosting circuit units from being rendered active at the same time by one clock signal. Since the boosting circuit unit is rendered active one by one by the provision of the delay element, current congregation from the power supply potential at the circuit element connected closest to the input terminal of the boosting circuit unit of the first stage can be prevented. Thus, a boosting circuit of a high boosting efficiency is achieved.
摘要翻译： 通过将来自OSC的时钟信号提供给串联连接的升压电路单元的四级，升压电路单元被激活。 延迟元件插入时钟信号的行中，以防止所有升压电路单元同时被一个时钟信号激活。 由于通过提供延迟元件使升压电路单元一个接一个地被激活，所以可以防止从最靠近第一级的升压电路单元的输入端子连接的电路元件处的电源电位的会聚。 因此，实现了高增压效率的升压电路。
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公开(公告)号：US06643207B2
公开(公告)日：2003-11-04
申请号：US10176633
申请日：2002-06-24
申请人： Masaaki Mihara
发明人： Masaaki Mihara
IPC分类号： G11C700
摘要： In a high-voltage detection circuit (10) for detecting a high voltage (VP) output from a high-voltage generation circuit (14), an output of the high-voltage generation circuit is dropped in voltage by a high-voltage drop circuit (13) to output a dropped voltage (VO), a reference-voltage generation circuit (11) generates a reference voltage (Vref) of a comparatively-high potential using the the high voltage (VP) as its power source, and a comparison circuit (12) compares the dropped voltage (VO) with the reference voltage (Vref) to control a high-voltage level.
摘要翻译： 在用于检测从高电压发生电路（14）输出的高电压（VP）的高电压检测电路（10）中，高压发生电路的输出由高压降电路 （13）输出下降电压（VO），基准电压生成电路（11）使用高电压（VP）作为其电源，生成比较高的电位的基准电压（Vref），并且进行比较 电路（12）将掉电电压（VO）与参考电压（Vref）进行比较，以控制高电压电平。
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公开(公告)号：US06344766B1
公开(公告)日：2002-02-05
申请号：US09515594
申请日：2000-02-29
申请人： Masaaki Mihara , Yasuhiko Taito
发明人： Masaaki Mihara , Yasuhiko Taito
IPC分类号： H03K190185
摘要： A voltage level converter circuit includes a first node, a second node having a voltage according to an input voltage, a P channel MOS transistor connected between the second node and the first node, turned on when the input voltage attains an L level, a third node to which a first voltage is supplied, a first N channel MOS transistor connected between the third node and a fourth node, turned on when the input voltage attains an H level, a second N channel MOS transistor connected between the first node and the fourth node, and having a gate to which an alleviate signal is supplied, a third N channel MOS transistor, and a level determination circuit for providing an alleviate signal according to the level of the first voltage.
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公开(公告)号：US6049243A
公开(公告)日：2000-04-11
申请号：US45568
申请日：1998-03-23
申请人： Masaaki Mihara , Yasuhiko Taito
发明人： Masaaki Mihara , Yasuhiko Taito
摘要： A voltage level converter circuit includes a first node, a second node having a voltage according to an input voltage, a P channel MOS transistor connected between the second node and the first node, turned on when the input voltage attains an L level, a third node to which a first voltage is supplied, a first N channel MOS transistor connected between the third node and a fourth node, turned on when the input voltage attains an H level, a second N channel MOS transistor connected between the first node and the fourth node, and having a gate to which an alleviate signal is supplied, a third N channel MOS transistor, and a level determination circuit for providing an alleviate signal according to the level of the first voltage.
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18.发明授权Circuit for resetting output of positive/negative high voltage generating circuit to VCC/VSS 失效用于将正/负高压发生电路的输出复位到VCC / VSS的电路
公开(公告)号：US5917354A
公开(公告)日：1999-06-29
申请号：US868974
申请日：1997-06-04
IPC分类号： G11C5/14 , G11C11/407 , G11C16/06 , H01L27/115 , H01L29/68 , H03K17/20
CPC分类号： G11C5/143 , Y10T307/675 , Y10T307/735
摘要： When a state of outputting a third power supply potential to an output node is switched to a state of outputting a second power supply potential, connection between a supply unit of the second power supply potential and the output node is made through a first P-channel MOSFET. Further, when the first P-channel MOSFET is turned off, i.e., when the third power supply potential is output to the output node, the third power supply potential is also applied to a gate of the first P-channel MOSFET. Therefore, even when the potential of the output node rises to the third power supply potential, this transistor is not turned on. Thus, the second power supply potential and the output node are appropriately and electrically isolated from each other. The circuit can be used with a flash memory to prevent over programming.
摘要翻译： 当向输出节点输出第三电源电位的状态切换到输出第二电源电位的状态时，第二电源电位的供给单元与输出节点之间的连接通过第一P沟道 MOSFET。 此外，当第一P沟道MOSFET截止时，即当第三电源电位输出到输出节点时，第三电源电位也被施加到第一P沟道MOSFET的栅极。 因此，即使输出节点的电位上升到第三电源电位，该晶体管也不会导通。 因此，第二电源电位和输出节点彼此适当且电气隔离。 该电路可与闪存一起使用，以防止过度编程。
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19.发明授权Power circuit with duty conversion circuit for driving a capacitive load 失效具有用于驱动电容性负载的占空比转换电路的电源电路
公开(公告)号：US5705895A
公开(公告)日：1998-01-06
申请号：US572664
申请日：1995-12-14
申请人： Masaaki Mihara
发明人： Masaaki Mihara
CPC分类号： H05B33/08 , Y02B20/325 , Y10S315/05
摘要： A power terminal is connected to a DC power source. A differential amplifier has primary and secondary input terminals and an output terminal, and a device applies a reference voltage to the secondary input terminal of the differential amplifier. A phase inverter has an input terminal connected to the output terminal of the differential amplifier and has primary and secondary output terminals that output two output signals of opposite phase. A push-pull drive circuit has primary and secondary input terminals connected to the primary and secondary output terminals of the phase inverter, and has primary and secondary output terminals connected to a switching element that alternately turns on and off by being driven by the two output signals of opposite phase that are provided from the output terminals of the phase inverter. An autotransformer has a tap connected to the power terminal and taps, provided at both sides of the tap connected to the power terminal, that are connected to the primary and secondary output terminals at the push-pull drive circuit, respectively. A capacitive load may be connected at both sides of the autotransformer. A positive feedback path connects one terminal of the autotransformer to the primary input terminal of the differential amplifier, and a sinusoidal AC voltage is applied to the capacitive load. A duty ratio conversion circuit automatically changes the duty ratio of drive signals for the push-pull drive circuit according to the resonance frequency that is determined by the inductance of the autotransformer and the capacitance of the capacitive load. The duty ratio conversion circuit is connected between the phase inverter and the push-pull drive circuit.
摘要翻译： 电源端子连接到直流电源。 差分放大器具有一次和二次输入端子和一个输出端子，并且器件将参考电压施加到差分放大器的次级输入端子。 一个相位逆变器的输入端连接到差分放大器的输出端，并具有输出相反相位的两个输出信号的初级和次级输出端。 推挽驱动电路具有连接到相位逆变器的主输出端和次输出端的初级和次级输入端，并且具有连接到开关元件的初级和次级输出端子，其通过由两个输出驱动而交替地导通和关断 从相变器的输出端子提供的反相信号。 自耦变压器具有连接到电源端子的抽头和分别连接到电源端子的抽头两侧的抽头，分别连接到推挽驱动电路的主输出端和次输出端。 电容性负载可以连接在自耦变压器的两侧。 正反馈路径将自耦变压器的一个端子连接到差分放大器的主输入端，并且正弦交流电压被施加到电容性负载。 占空比转换电路根据由自耦变压器的电感和容性负载的电容确定的谐振频率自动改变推挽驱动电路的驱动信号的占空比。 占空比转换电路连接在相位逆变器和推挽驱动电路之间。
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20.发明授权Content addressable memory combining match comparisons of a plurality of cells 失效内容可寻址存储器组合多个单元的比较比较
公开(公告)号：US5130945A
公开(公告)日：1992-07-14
申请号：US551268
申请日：1990-07-12
CPC分类号： G11C15/04 , G11C15/043
摘要： Each match line is connected to a plurality of CAM cells constituting a CAM array. The respective CAM cells store data applied through a bit line and an inverted-bit line in its data storage portion when selected by a word line. The stored data are applied to a data comparison portion to be compared with retrieval data applied through the bit line and the inverted-bit line, thereby detecting match or mismatch therebetween. A comparison result of the data comparison portion is first stored in a capacitance element in the form of charge. In order to prevent escape of the information stored in the capacitance element, a blocking means blocks a part of a charge and discharge path for the capacitance element. A charge transfer means provided between the capacitance element and the match line transfers a certain amount of charge from either one to the other when information of mismatch is stored in the capacitance element. This causes fluctuation of charge potential on the match line. The fluctuation of potential on the match line depends on the number of mismatched CAM cells out of a plurality of CAM cells connected to the match line. Therefore, detection of potential on the match line permits detecting the number of mismatched CAM cells.
摘要翻译： 每个匹配线连接到构成CAM阵列的多个CAM单元。 当通过字线选择时，相应的CAM单元存储在其数据存储部分中通过位线和反相位线施加的数据。 将存储的数据应用于数据比较部分，以与通过位线和反向位线施加的检索数据进行比较，从而检测它们之间的匹配或失配。 数据比较部分的比较结果首先以电荷的形式存储在电容元件中。 为了防止存储在电容元件中的信息的逸出，阻塞装置阻挡电容元件的充电和放电路径的一部分。 当在电容元件中存储不匹配的信息时，设置在电容元件和匹配线之间的电荷转移装置将一定量的电荷从两者之一传递到另一个。 这导致匹配线上的电荷电位波动。 匹配线上的电位波动取决于连接到匹配线的多个CAM单元中不匹配的CAM单元的数量。 因此，匹配线上的电位检测允许检测不匹配的CAM单元的数量。
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