公开(公告)号：US07824188B2

公开(公告)日：2010-11-02

申请号：US12630290

申请日：2009-12-03

申请人： Yuji Yokoyama

发明人： Yuji Yokoyama

IPC分类号： H01R12/00

CPC分类号： H05K7/1061

摘要： A socket for an electric component includes: a socket main body having a receiving portion which receives an electric component such as an IC package; a socket cover supported to be capable of turning by a first turning shaft provided in a vicinity of one side end of the socket main body to turn to thereby open or close the housing portion; and a radiating member mounted to the socket cover and is in contact with the electric component received in the receiving portion to radiate heat from the electric component in a state of the socket cover being closed. The socket cover has an opening portion formed in a position corresponding to the receiving portion of the socket main body in the closed state, and the radiating member is supported to be capable of turning by a second turning shaft parallel to the first turning shaft in the opening of the socket cover.

摘要翻译： 一种用于电气部件的插座包括：插座主体，具有容纳诸如IC封装的电气部件的接收部分; 插座盖被支撑成能够通过设置在插座主体的一个侧端附近的第一转动轴转动，从而打开或关闭壳体部; 以及散热构件，其安装到所述插座盖并且与所述接收部分中容纳的电气部件接触，以在所述插座盖被封闭的状态下从所述电气部件辐射热量。 插座盖具有在关闭状态下形成在与插座主体的容纳部相对应的位置的开口部，并且散热构件被支撑为能够通过平行于第一转动轴的第二转动轴在第 打开插座盖。

公开(公告)号：US20060219677A1

公开(公告)日：2006-10-05

申请号：US11392803

申请日：2006-03-30

申请人： Kanji Matsutani ,  Masaki Mashiko ,  Yuji Yokoyama ,  Mieko Akaba ,  Hiroshi Yagisawa ,  Masao Akatsuka ,  Shoichi Fukuda

发明人： Kanji Matsutani ,  Masaki Mashiko ,  Yuji Yokoyama ,  Mieko Akaba ,  Hiroshi Yagisawa ,  Masao Akatsuka ,  Shoichi Fukuda

IPC分类号： B23K26/38

CPC分类号： B21G1/08 ,  A61B17/06066 ,  A61B2017/00526 ,  A61B2017/061 ,  B23K26/389

摘要： A method for manufacturing an eyeless needle by which a satisfactory hole can be formed in the end surface of a fine suture needle having a needle diameter less than 150 micrometers is proposed. In a method for manufacturing an eyeless needle by forming a hole for inserting and fixing one end of a suture thread by caulking in the end surface of the eyeless suture needle made of stainless steel, the hole is formed by irradiating the end surface of a needle material thicker by 6 to 20 micrometers than a desired needle diameter of the suture needle less than 150 micrometers with one shot of a laser beam, and subsequently, a portion thicker than the desired needle diameter is removed by electrolytic polishing or chemical polishing.

摘要翻译： 提出了一种制造无眼针的方法，通过该方法可以在针直径小于150微米的精细缝合针的端面中形成令人满意的孔。 在通过在由不锈钢制成的无眼缝合针的端面中铆接而形成用于插入和固定缝合线的一端的孔的方法中，通过照射针的端面而形成孔 通过电击抛光或化学抛光除去比单次激光束小于150微米的缝合针的期望针直径比所需针直径更大6至20微米的材料，随后通过电解抛光或化学抛光除去比所需针直径更厚的部分。

公开(公告)号：US06735129B2

公开(公告)日：2004-05-11

申请号：US10153525

申请日：2002-05-24

申请人： Hiroshi Akasaki ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Masatoshi Hasegawa ,  Kozaburo Kurita

发明人： Hiroshi Akasaki ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Masatoshi Hasegawa ,  Kozaburo Kurita

IPC分类号： G11C700

CPC分类号： G11C7/1066 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1072 ,  G11C2207/104

摘要： In a semiconductor integrated circuit device that includes macro cells (circuit blocks that can be designed independently) such as a storage circuit and operates synchronously with an external clock, total delay time from signal input to output is reduced and the speed of operation is increased. In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks that receive input signals in response to a first timing signal based on a clock signal, and a second circuit block that forms output signals in response to a second timing signal based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.

摘要翻译： 在包括诸如存储电路的宏单元（可独立设计的电路块）并且与外部时钟同步地操作的半导体集成电路器件中，从信号输入到输出的总延迟时间减少，并且操作速度增加。 在具有串联耦合用于信号传输并且其整个操作由时钟信号控制的多个电路块的半导体集成电路器件中，半导体集成电路器件包括响应于基于第一定时信号接收输入信号的第一电路块 时钟信号和响应于基于时钟信号的第二定时信号形成输出信号的第二电路块，第一定时信号和第二定时信号之间的时间差被设置为该周期的非整数倍 的时钟信号。

公开(公告)号：US06285045B1

公开(公告)日：2001-09-04

申请号：US08890991

申请日：1997-07-10

申请人： Kazuo Itabashi ,  Osamu Tsuboi ,  Yuji Yokoyama ,  Kenichi Inoue ,  Koichi Hashimoto ,  Wataru Futo

发明人： Kazuo Itabashi ,  Osamu Tsuboi ,  Yuji Yokoyama ,  Kenichi Inoue ,  Koichi Hashimoto ,  Wataru Futo

IPC分类号： H01L2710

CPC分类号： H01L27/10852 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/10805 ,  H01L27/10817 ,  H01L28/91

摘要： A semiconductor memory device comprising: a first insulating film covering the upper and side surfaces of a gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the second insulating film and reaching the impurity diffusion regions; a conductive plug embedded in one of the contact holes; a third insulating film formed on the second insulating film covering the conductive plug, and having a first aperture on the other contact hole; a bit line formed on the third insulating film and connected to the other impurity diffusion region through the first aperture and the other contact hole; a fourth insulating film covering the upper and side surfaces of the bit line; a second aperture formed through the third insulating film in alignment with the fourth insulating film covering the side surface of the bit line; a storage electrode formed to extend over the bit line, insulated from the bit line by the third and fourth insulating films, and electrically connected to the conductive plug through the second aperture.

摘要翻译： 一种半导体存储器件，包括：覆盖栅电极的上表面和侧表面的第一绝缘膜; 形成在覆盖所述第一绝缘膜的所述基板上的第二绝缘膜; 形成在所述第二绝缘膜上并到达所述杂质扩散区的一对接触孔; 嵌入在所述接触孔之一中的导电插塞; 第三绝缘膜，形成在覆盖所述导电插塞的所述第二绝缘膜上，并且在所述另一个接触孔上具有第一孔; 形成在第三绝缘膜上并通过第一孔和另一个接触孔连接到另一个杂质扩散区的位线; 覆盖位线的上表面和侧表面的第四绝缘膜; 与覆盖所述位线的侧面的所述第四绝缘膜对准的通过所述第三绝缘膜形成的第二孔; 存储电极，其形成为在所述位线上延伸，通过所述第三和第四绝缘膜与所述位线绝缘，并且通过所述第二孔电连接到所述导电插塞。

公开(公告)号：US5787043A

公开(公告)日：1998-07-28

申请号：US394765

申请日：1995-02-27

申请人： Takashi Akioka ,  Yuji Yokoyama ,  Atsushi Hiraishi ,  Masahiro Iwamura ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Koichi Motohashi

发明人： Takashi Akioka ,  Yuji Yokoyama ,  Atsushi Hiraishi ,  Masahiro Iwamura ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Koichi Motohashi

IPC分类号： G11C29/00 ,  G11C11/401 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/844

摘要： A semiconductor device is provided which comprises a memory mat formed by dividing a memory into a plurality of blocks and a circuit arrangement disposed at every memory mat block for generating access suppression signals at least for defective memory cells within that block. Using this arrangement, the access speed to a redundant memory cell array for relieving the defects is increased so that a semiconductor memory device capable of a high speed operation is obtained.

摘要翻译： 提供了一种半导体器件，其包括通过将存储器分成多个块形成的存储器衬垫和布置在每个存储器块块处的电路布置，用于至少对该块内的缺陷存储器单元产生访问抑制信号。 使用这种布置，增加了用于消除缺陷的冗余存储单元阵列的访问速度，从而获得能够进行高速操作的半导体存储器件。

公开(公告)号：US5675548A

公开(公告)日：1997-10-07

申请号：US608605

申请日：1996-02-29

申请人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

发明人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

IPC分类号： G11C7/10 ,  G11C8/10 ,  H03K19/0948 ,  G11C8/00

CPC分类号： H03K19/0948 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10

摘要： An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuit which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.

摘要翻译： 提供了对于使用例如公共NMOS来接收多个逻辑解码器门的一个输入的半导体存储器电路中的解码器特别有效的装置，其包括多个逻辑门，每个逻辑门具有用于分别接收第一输入的第一输入端 信号，并且每个都耦合到公共节点。 在一个实施例中，第一和第二开关元件也耦合到公共节点。 第一和第二开关元件都耦合到第二输入端子，用于接收多个逻辑门公共的第二输入信号，并且它们都响应于第二输入信号互相互补。 还提供了一种用于这种半导体存储器电路的改进的读/写布置，该电路包括用于在写入操作期间公共读取线与数据线的连接的电路。 这通过在写入期间去除公共读取线的负载来增强写入速度。

公开(公告)号：US20130309529A1

公开(公告)日：2013-11-21

申请号：US13981849

申请日：2012-01-12

申请人： Yuji Yokoyama ,  Yasushi Nakagiri

发明人： Yuji Yokoyama ,  Yasushi Nakagiri

IPC分类号： H01M10/52

CPC分类号： H01M10/52 ,  H01M2/022 ,  H01M2/0413 ,  H01M2/1241 ,  H01M10/0525

摘要： Disclosed is a cylindrical battery including: a cylindrical wound electrode group including sheet-like positive and negative electrodes, and a separator interposed therebetween; a bottomed cylindrical battery case having an opening and accommodating the electrode group; and a sealing unit sealing the opening. The electrode group has, at its center portion, a cavity extending in the axis direction thereof. The sealing unit includes a terminal plate having a vent hole, and a valve plate made of an electrically conductive material. The valve plate includes first and second rupturable portions each configured to be ruptured by an increase in the internal pressure of the battery case. The first rupturable portion is provided so as to surround a first region of the valve plate facing the cavity. The second rupturable portion is provided so as to surround a second region of the valve plate. The second region includes the first region.

摘要翻译： 公开了一种圆柱形电池，包括：包括片状正极和负极的圆柱形卷绕电极组和插入其间的隔膜; 具有开口并容纳电极组的有底圆柱形电池盒; 以及密封单元密封开口。 电极组在其中心部分具有沿其轴向延伸的空腔。 密封单元包括具有通气孔的端子板和由导电材料制成的阀板。 阀板包括第一和第二可破裂部分，每个可破裂部分被构造成通过电池壳体的内部压力的增加而破裂。 第一可破裂部分设置成围绕面对空腔的阀板的第一区域。 第二可破裂部分设置成围绕阀板的第二区域。 第二个地区包括第一个地区。

公开(公告)号：US08093931B2

公开(公告)日：2012-01-10

申请号：US12420253

申请日：2009-04-08

申请人： Toshio Shinomiya ,  Akio Koyama ,  Yuji Yokoyama

发明人： Toshio Shinomiya ,  Akio Koyama ,  Yuji Yokoyama

IPC分类号： H03L7/00

CPC分类号： H03K17/223 ,  G06F1/24

摘要： In a semiconductor integrated circuit device generating internal power from external power, an abnormal operation may occur due to an indefinite state of a control signal when the external power is applied and the internal power rises. The semiconductor integrated circuit includes an internal power generating circuit, a control circuit receiving internal power and supplying a first control signal, and a power-on reset circuit generating a reset signal at rising of the internal power. When internal power rises, the reset signal masks an indefinite state of the first control signal supplied from the control circuit.

摘要翻译： 在从外部电力产生内部电力的半导体集成电路装置中，当施加外部电力并且内部电力上升时，可能由于控制信号的不确定状态而发生异常操作。 半导体集成电路包括内部发电电路，接收内部电力并提供第一控制信号的控制电路，以及在内部电力上升时产生复位信号的上电复位电路。 当内部电源上升时，复位信号屏蔽从控制电路提供的第一控制信号的不确定状态。

公开(公告)号：US07151025B2

公开(公告)日：2006-12-19

申请号：US10388447

申请日：2003-03-17

申请人： Kazuo Itabashi ,  Osamu Tsuboi ,  Yuji Yokoyama ,  Kenichi Inoue ,  Koichi Hashimoto ,  Wataru Futo

发明人： Kazuo Itabashi ,  Osamu Tsuboi ,  Yuji Yokoyama ,  Kenichi Inoue ,  Koichi Hashimoto ,  Wataru Futo

IPC分类号： H01O21/8242

CPC分类号： H01L27/10852 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/10805 ,  H01L27/10817 ,  H01L28/91

摘要： A method of manufacturing a semiconductor device on a semiconductor substrate having a first region and a second region. This method beings by forming a transistor in the first region of said semiconductor substrate. This transistor includes a pair of impurity diffusion regions and a gate electrode. Then forming a first insulating film over the first and second regions with this first insulating film covering the transistor in the first region. Thereafter, patterning the first insulating film to selectively remove the first insulating film in the second region. Then forming a second insulating film over the first and second regions. Thereafter, forming at least one contact hole through the second and first insulating film. The contact hole reaches one of the impurity diffusion regions. Finally, forming a conductive layer in the contact hole.

摘要翻译： 一种在具有第一区域和第二区域的半导体衬底上制造半导体器件的方法。 该方法通过在所述半导体衬底的第一区域中形成晶体管来实现。 该晶体管包括一对杂质扩散区和栅电极。 然后在第一和第二区域上形成第一绝缘膜，该第一绝缘膜覆盖第一区域中的晶体管。 此后，图案化第一绝缘膜以选择性地去除第二区域中的第一绝缘膜。 然后在第一和第二区域上形成第二绝缘膜。 此后，通过第二和第一绝缘膜形成至少一个接触孔。 接触孔到达杂质扩散区域中的一个。 最后，在接触孔中形成导电层。

公开(公告)号：US5777952A

公开(公告)日：1998-07-07

申请号：US678267

申请日：1996-07-11

申请人： Hajime Nishimura ,  Atsushi Ichikawa ,  Akio Yabe ,  Yuji Yokoyama

发明人： Hajime Nishimura ,  Atsushi Ichikawa ,  Akio Yabe ,  Yuji Yokoyama

IPC分类号： G11B11/10 ,  G11B11/105 ,  G11B11/00

CPC分类号： G11B11/10558 ,  G11B11/1056

摘要： A bias magnet unit has a permanent magnet that applies a bias magnetic field to an optical spot on a magneto-optical disk. A driving coil rotates the magnet in order to change a polarity of the bias magnetic field. A sensor detects the intensity and polarity of the bias magnetic field to confirm the rotational position of the magnet after it has been rotated. A linkage structure that is connected between a magnet holder of the magnet unit and the housing has arms that drive the magnet unit between two positions, one in which the magneto-optical disk cartridge can be inserted into the device and another in which the disk is loaded onto the spindle motor for recording/playback. Overall, the components of the device cooperate structurally to provide a relatively thin device structure having low power consumption.

摘要翻译： 偏置磁体单元具有向磁光盘上的光点施加偏置磁场的永磁体。 驱动线圈使磁体旋转，以改变偏磁场的极性。 传感器检测偏磁场的强度和极性，以确认磁体旋转后的旋转位置。 连接在磁体单元的磁体保持器和壳体之间的连接结构具有在两个位置之间驱动磁体单元的臂，其中可以将磁光盘盒插入到该装置中，其中磁盘 加载到主轴电机上进行记录/播放。 总体而言，该装置的部件在结构上配合以提供具有低功耗的较薄的装置结构。