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37 条记录 (耗时 0.033 秒)

    Plasma processing apparatus and method
    11.
    发明授权
    Plasma processing apparatus and method 失效
    等离子体处理装置及方法

    公开(公告)号：US06274507B1

    公开(公告)日：2001-08-14

    申请号：US09226723

    申请日：1999-01-07

    申请人： Masaki Narita ,  Yukimasa Yoshida ,  Kei Hattori ,  Katsuya Okumura

    发明人： Masaki Narita ,  Yukimasa Yoshida ,  Kei Hattori ,  Katsuya Okumura

    IPC分类号： H01L2131

    CPC分类号： H01L21/67017 ,  C23C14/564 ,  C23C16/4401 ,  C23C16/54 ,  H01J37/32743 ,  H01J37/32834 ,  Y10S438/907 ,  Y10S438/908 ,  Y10S438/909

    摘要： A semiconductor processing apparatus includes a load chamber, an unload chamber, a common transfer chamber, a first process chamber, and a second process chamber, which are connected via gate valves. The load and unload chambers are connected to a first vacuum-exhaust mechanism including a common dry pump. The common transfer chamber is connected to a second vacuum-exhaust mechanism including a dry pump. The first and second processes chambers are connected to a third vacuum-exhaust mechanism including a common dry pump, and first and second turbo molecular pumps. The processing apparatus includes a controller which can drive and stop the dry pumps independently of each other in coordination with open/closed switching of the gate valves, while keeping the turbo molecular pumps driven.

    摘要翻译： 半导体处理装置包括通过闸阀连接的装载室，卸载室，公共传送室，第一处理室和第二处理室。 装载和卸载室连接到包括普通干式泵的第一真空排气机构。 公共传送室连接到包括干式泵的第二真空排气机构。 第一和第二处理室连接到包括普通干式泵以及第一和第二涡轮分子泵的第三真空排气机构。 处理装置包括控制器，其可以在保持涡轮分子泵被驱动的同时，与闸阀的打开/关闭切换协调地彼此独立地驱动和停止干式泵。

    Low pressure and low power C1.sub.2 /HC1 process for sub-micron metal etching
    13.
    发明授权
    Low pressure and low power C1.sub.2 /HC1 process for sub-micron metal etching 失效
    低压和低功率C12 / HC1工艺用于亚微米金属蚀刻

    公开(公告)号：US5976986A

    公开(公告)日：1999-11-02

    申请号：US689174

    申请日：1996-08-06

    申请人： Munir D. Naeem ,  Stuart M. Burns ,  Rosemary Christie ,  Virinder Grewal ,  Walter W. Kocon ,  Masaki Narita ,  Bruno Spuler ,  Chi-Hua Yang

    发明人： Munir D. Naeem ,  Stuart M. Burns ,  Rosemary Christie ,  Virinder Grewal ,  Walter W. Kocon ,  Masaki Narita ,  Bruno Spuler ,  Chi-Hua Yang

    IPC分类号： C23F4/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213

    CPC分类号： H01L21/32136 ,  C23F4/00

    摘要： RIE of metallization is achieved at low power and low pressure using Cl.sub.2 and HCl as reactant species by creating a transformer coupled plasma with power applied to electrodes positioned both above and below a substrate with metallization thereon to be etched. Three layer metallizations which include bulk aluminum or aluminum alloy sandwiched between barrier layers made from, for example, Ti/TiN, are etched in a three step process wherein relatively lower quantities of Cl.sub.2 are used in the plasma during etching of the barrier layers and relatively higher quantities of Cl.sub.2 are used during etching of the bulk aluminum or aluminum alloy layer. The ratio of etchants Cl.sub.2 and HCl and an inert gas, such as N.sub.2 are controlled in a manner such that a very thin side wall layer (10-100 .ANG.) of reaction byproducts created during RIE are deposited on the side walls of trenches formed in the metallization during etching. The side wall layer improves the isotropic nature of the etch such that submicron metallization lines with defect free side walls are formed. Hydrogen (H.sub.2) can be added to the plasma and will act to reduce corrosion.

    摘要翻译： 通过使用Cl2和HCl作为反应物种来实现金属化的RIE，通过产生变压器耦合的等离子体，其功率施加到位于要蚀刻的金属化的衬底上方和下方的电极上。 夹在由例如Ti / TiN制成的阻挡层之间的主体铝或铝合金的三层金属化被蚀刻在三步法中，其中在蚀刻阻挡层期间在等离子体中使用相对较少量的Cl 2，并且相对 在大量铝或铝合金层的蚀刻期间使用较高量的Cl 2。 蚀刻剂Cl2和HCl以及惰性气体（例如N 2）的比例被控制为使得在RIE期间产生的反应副产物的非常薄的侧壁层（10-100）沉积在形成的沟槽的侧壁上 蚀刻期间的金属化。 侧壁层改善了蚀刻的各向同性，从而形成具有无缺陷侧壁的亚微米金属化线。 可以将氢（H2）加入到等离子体中，并且起作用以减少腐蚀。

    Method of fabricating semiconductor device with reduced pitch
    15.
    发明授权
    Method of fabricating semiconductor device with reduced pitch 失效
    半导体器件的制造方法

    公开(公告)号：US07732338B2

    公开(公告)日：2010-06-08

    申请号：US12251791

    申请日：2008-10-15

    申请人： Masaki Narita

    发明人： Masaki Narita

    IPC分类号： H01L21/311

    CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/76224 ,  H01L27/11521

    摘要： A method of fabricating a semiconductor device includes depositing a first film on a workpiece film so that a resist is formed on the first film, processing the first film with the resist serving as a mask, depositing a second film along the first film, processing the second film so that the second film is left only on a sidewall of the first film, depositing a third film on the substrate, exposing a sidewall of the second film, depositing a fourth film along the sidewall and an upper surface of the third film, removing the fourth film except for only its part on the sidewall of the second film, depositing a fifth film on the substrate, planarizing the second to fifth films so that the upper surfaces of the films are exposed, and processing the workpiece film while the second and fifth films serve as a mask.

    摘要翻译： 一种制造半导体器件的方法包括在工件膜上沉积第一膜，使得在第一膜上形成抗蚀剂，用抗蚀剂作为掩模处理第一膜，沿着第一膜沉积第二膜， 第二膜，使得第二膜仅留在第一膜的侧壁上，在基板上沉积第三膜，暴露第二膜的侧壁，沿着侧壁沉积第四膜和第三膜的上表面， 除去除了第二膜的侧壁之外的第四膜的第四膜，在基板上沉积第五膜，平面化第二至第五膜，使得膜的上表面暴露，并且处理工件膜，而第二膜 第五部电影作为面具。

    Method of manufacturing semiconductor device
    16.
    发明申请
    Method of manufacturing semiconductor device 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20060057785A1

    公开(公告)日：2006-03-16

    申请号：US10994239

    申请日：2004-11-23

    申请人： Tomoya Satonaka ,  Toshiyuki Sasaki ,  Masaki Narita

    发明人： Tomoya Satonaka ,  Toshiyuki Sasaki ,  Masaki Narita

    IPC分类号： H01L21/00 ,  H01L21/84

    CPC分类号： H01L21/32137 ,  H01L21/28044 ,  H01L21/32139 ,  H01L21/76229

    摘要： Disclosed is a method of manufacturing a semiconductor device, comprising introducing a work piece comprising a semiconductor substrate, a gate insulation film formed on the semiconductor substrate, and a gate electrode film formed on the gate insulation film, into a chamber, and forming a gate electrode by selectively etching the gate electrode film relative to the gate insulation film by anisotropic dry etching in the chamber, wherein forming the gate electrode includes etching the gate electrode film under a condition that a residence time of an etching gas in the chamber is 100 milliseconds or shorter, at least after a part of the gate insulation film is exposed.

    摘要翻译： 公开了一种制造半导体器件的方法，包括将形成在半导体衬底上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极膜的工件包括半导体衬底，形成在栅极绝缘膜上的栅电极膜， 电极，其通过在室中的各向异性干蚀刻相对于栅极绝缘膜选择性蚀刻栅电极膜，其中形成栅电极包括在室内的蚀刻气体的停留时间为100毫秒的条件下蚀刻栅电极膜 或更短，至少在栅极绝缘膜的一部分露出之后。

    Semiconductor device and method of manufacturing the same
    17.
    发明申请
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US20050023592A1

    公开(公告)日：2005-02-03

    申请号：US10688965

    申请日：2003-10-21

    申请人： Toshiyuki Sasaki ,  Masaki Narita

    发明人： Toshiyuki Sasaki ,  Masaki Narita

    IPC分类号： H01L21/28 ,  H01L21/3065 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/76

    CPC分类号： H01L21/823437

    摘要： There are provided a gate dielectric film formed on a semiconductor substrate; a gate electrode including: a first electrode layer formed on the gate dielectric film, a dielectric film having a thickness of 5 Å or more and 100 Å or less, and formed on the first electrode layer, and a second electrode layer formed on the dielectric film; and a source and drain regions formed in the semiconductor substrate at both sides of the gate electrode.

    摘要翻译： 提供了形成在半导体衬底上的栅介质膜; 栅电极，包括：形成在所述栅极电介质膜上的第一电极层，形成在所述第一电极层上的厚度为或更大且小于或等于或小于100埃的电介质膜，以及形成在所述电介质上的第二电极层 电影; 以及在栅电极的两侧形成在半导体衬底中的源区和漏区。

    Dry etching method
    19.
    发明授权
    Dry etching method 失效
    干蚀刻法

    公开(公告)号：US06383942B1

    公开(公告)日：2002-05-07

    申请号：US09522168

    申请日：2000-03-09

    申请人： Masaki Narita ,  Hiroshi Sugiura

    发明人： Masaki Narita ,  Hiroshi Sugiura

    IPC分类号： H01L2100

    CPC分类号： C23F4/00 ,  H01L21/32136

    摘要： A dry etching method is disclosed for use in patterning a stacked film of a metal film containing aluminum as the base component and a thin film including at least one of titanium and titanium nitride. In this method, the thin film is dry-etched using a first etching gas (a mixture of CF4 gas, Ar gas and Cl gas) having a gas composition for preventing the metal film from being processed. The metal film is then dry-etched using a second etching gas (a mixture of Cl gas and BCl3 gas) having a gas composition other than the first etching gas.

    摘要翻译： 公开了用于图案化含有铝作为基底成分的金属膜的叠层膜和包括钛和氮化钛中的至少一种的薄膜的干蚀刻方法。 在该方法中，使用具有防止金属膜被处理的气体组成的第一蚀刻气体（CF4气体，Ar气体和Cl气体的混合物）对该薄膜进行干蚀刻。 然后使用除了第一蚀刻气体之外的气体组成的第二蚀刻气体（Cl气体和BCl 3气体的混合物）对金属膜进行干法蚀刻。