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136 条记录 (耗时 0.043 秒)

    Clock routing in multiple channel modules and bus systems
    16.
    发明授权
    Clock routing in multiple channel modules and bus systems 失效
    多通道模块和总线系统中的时钟路由

    公开(公告)号：US06590781B2

    公开(公告)日：2003-07-08

    申请号：US09817828

    申请日：2001-03-26

    申请人： Ravindranath T. Kollipara ,  David Nguyen ,  Belgacem Haba

    发明人： Ravindranath T. Kollipara ,  David Nguyen ,  Belgacem Haba

    IPC分类号： H05K702

    CPC分类号： G11C5/04 ,  G06F13/409 ,  G11C5/00 ,  H05K1/023 ,  H05K1/117 ,  H05K1/141 ,  H05K1/147 ,  H05K1/148 ,  H05K7/1459 ,  H05K2201/10189

    摘要： An apparatus is provided, which includes a memory interface circuit, a clock signal generating circuit, and a plurality of memory circuits. The memory circuits are operatively coupled and arranged in an order on a plurality of memory modules, such that the memory module positioned at the beginning of the order is coupled to an output of the clock signal generating circuit and the memory interface circuit. The memory module that is positioned at the end of the order is unique in that it includes a clock signal terminating circuit connected to the last memory integrated circuit. With this configuration, a clock loop is formed by directly routing the clock signal from the output of the clock signal generating circuit through each of the memory modules in the order (without connecting to any of the intervening memory integrated circuits) to the memory integrated circuit positioned at the end of the order. Then, the clock signal is asserted on the previous memory modules by routing it back through the memory integrated circuits thereon, in reverse order to the memory integrated circuit positioned at the beginning of the order and from there to the memory interface circuit. To complete the clock loop, the clock signal is again asserted by routing it from the memory interface circuit back through the memory integrated circuits in order to the memory integrated circuit positioned at the end of the order. Finally, the clock signal is terminated at the clock signal terminating circuit on the memory module positioned at the end of the order.

    摘要翻译： 提供了一种装置，其包括存储器接口电路，时钟信号发生电路和多个存储器电路。 存储器电路被可操作地耦合并按照多个存储器模块的顺序排列，使得位于该命令开始处的存储器模块被耦合到时钟信号发生电路和存储器接口电路的输出端。 定位在订单结尾的存储器模块是唯一的，因为它包括连接到最后存储器集成电路的时钟信号终端电路。 利用这种配置，通过将时钟信号发生电路的输出的时钟信号通过每个存储器模块以顺序（不连接到任何中间存储器集成电路）直​​接路由到存储器集成电路而形成时钟环路 定位在订单结束。 然后，时钟信号在先前的存储器模块上通过其上的存储器集成电路将其重新布置，以与定位在订单开始处的存储器集成电路相反，并且从那里到存储器接口电路。 为了完成时钟环路，时钟信号通过将存储器接口电路从存储器集成电路重新路由到存储器集成电路定位在订单结束处而被再次断言。 最后，时钟信号终止在位于订单结束的存储器模块上的时钟信号终端电路。

    METHOD AND SYSTEM FOR FUND VISUALIZATION
    18.
    发明申请
    METHOD AND SYSTEM FOR FUND VISUALIZATION 有权
    基于可视化的方法和系统

    公开(公告)号：US20130138721A1

    公开(公告)日：2013-05-30

    申请号：US13307451

    申请日：2011-11-30

    申请人： Paul O'Connell ,  David Nguyen ,  George White ,  Matt Crist ,  Michael Tuccinard ,  Matthew Stuehler ,  Michael Novak

    发明人： Paul O'Connell ,  David Nguyen ,  George White ,  Matt Crist ,  Michael Tuccinard ,  Matthew Stuehler ,  Michael Novak

    IPC分类号： G06F15/16

    CPC分类号： G06Q40/06

    摘要： A finds comparison tool is provided that includes a presentation tier providing a plurality of interfaces for interacting with a plurality of client applications. The presentation tier allows the client applications to send requests for a plurality of analytics to be performed regarding comparing the performance of one or more funds or portfolios as well allowing mobile-based client applications and web-based client applications to communicate with the funds comparison tool. An application tier processes the requests sent by the client applications by providing the data used by the client applications, storing and retrieving of session data, and an interface for the analytics information captured during sessions so as to allow a visualization of the analytics used in the comparison of the one or more funds or portfolios.

    摘要翻译： 提供了一种查找比较工具，其包括提供用于与多个客户端应用程序交互的多个界面的表示层。 表示层允许客户端应用程序发送关于比较一个或多个资金或组合的性能的多个分析请求，并允许基于移动的客户端应用程序和基于Web的客户端应用程序与资金比较工具进行通信 。 应用程序层通过提供客户端应用程序使用的数据，存储和检索会话数据以及用于在会话期间捕获的分析信息的界面来处理客户端应用程序发送的请求，以便允许可视化在 比较一个或多个基金或投资组合。

    Extended USB plug, USB PCBA, and USB flash drive with dual-personality for embedded application with mother boards
    19.
    发明授权
    Extended USB plug, USB PCBA, and USB flash drive with dual-personality for embedded application with mother boards 失效
    扩展USB插头，USB PCBA和USB闪存驱动器，具有双重个性，可与母板进行嵌入式应用

    公开(公告)号：US08297987B2

    公开(公告)日：2012-10-30

    申请号：US13211100

    申请日：2011-08-16

    申请人： David Nguyen ,  Nan Nan ,  Jim Chin-Nan Ni ,  Frank I-Kang Yu ,  Abraham C. Ma ,  Ming-Shiang Shen

    发明人： David Nguyen ,  Nan Nan ,  Jim Chin-Nan Ni ,  Frank I-Kang Yu ,  Abraham C. Ma ,  Ming-Shiang Shen

    IPC分类号： H05K5/03

    CPC分类号： G06K19/07732

    摘要： An extended universal serial bus (USB) storage device is described herein. According to one embodiment, an extended USB storage device includes a printed circuit board assembly (PCBA) having a flash memory device and a flash controller mounted thereon, and an extended USB connector plug coupled to the PCBA for providing a USB compatible interface between an external device and the flash memory device and the flash controller, wherein the extended USB connector plug includes a first end used to couple to the external device and a second end coupled to the flash memory device and the flash controller. The extended USB connector plug includes multiple communication interfaces. Other methods and apparatuses are also described.

    摘要翻译： 本文描述了扩展通用串行总线（USB）存储设备。 根据一个实施例，扩展的USB存储设备包括具有闪存设备和安装在其上的闪存控制器的印刷电路板组件（PCBA），以及耦合到PCBA的扩展USB连接器插头，用于在外部 设备和闪存设备和闪存控制器，其中扩展的USB连接器插头包括用于耦合到外部设备的第一端和耦合到闪存设备和闪存控制器的第二端。 扩展的USB连接器插头包括多个通信接口。 还描述了其它方法和装置。