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19 条记录 (耗时 0.025 秒)

    High selectivity and residue free process for metal on thin dielectric gate etch application
    11.
    发明授权
    High selectivity and residue free process for metal on thin dielectric gate etch application 失效
    在薄介质栅极蚀刻应用上金属的高选择性和无残留的工艺

    公开(公告)号：US06933243B2

    公开(公告)日：2005-08-23

    申请号：US10279320

    申请日：2002-10-23

    申请人： Meihua Shen ,  Yan Du ,  Nicolas Gani ,  Oranna Yauw ,  Hakeem M. Oluseyi

    发明人： Meihua Shen ,  Yan Du ,  Nicolas Gani ,  Oranna Yauw ,  Hakeem M. Oluseyi

    IPC分类号： H01L21/28 ,  H01L21/3213 ,  H01L29/49 ,  H01L21/302

    CPC分类号： H01L21/28088 ,  H01L21/32136 ,  H01L29/4966

    摘要： Methods for etching electrodes formed directly on gate dielectrics are provided. In one aspect, an etch process is provided which includes a main etch step, a soft landing step, and an over etch step. In another aspect, a method is described which includes performing a main etch having good etch rate uniformity and good profile uniformity, performing a soft landing step in which a metal/metal barrier interface can be determined, and performing an over etch step to selectively remove the metal barrier without negatively affecting the dielectric. In another aspect, a method is provided which includes a first non-selective etch chemistry for bulk removal of electrode material, a second intermediate selective etch chemistry with end point capability, and then a selective etch chemistry to stop on the gate dielectric.

    摘要翻译： 提供了直接形成在栅极电介质上的蚀刻电极的方法。 在一个方面，提供了一种蚀刻工艺，其包括主蚀刻步骤，软着色步骤和过蚀刻步骤。 在另一方面，描述了一种方法，其包括执行具有良好蚀刻速率均匀性和良好轮廓均匀性的主蚀刻，执行软着色步骤，其中可以确定金属/金属屏障界面，以及执行过蚀刻步骤以选择性地去除 金属屏障，而不会对电介质产生负面影响。 在另一方面，提供了一种方法，其包括用于大量去除电极材料的第一非选择性蚀刻化学品，具有端点能力的第二中间选择性蚀刻化学品，然后选择蚀刻化学物质停止在栅极电介质上。

    Alternative method for advanced CMOS logic gate etch applications
    13.
    发明授权
    Alternative method for advanced CMOS logic gate etch applications 失效
    先进的CMOS逻辑门蚀刻应用的替代方法

    公开(公告)号：US07910488B2

    公开(公告)日：2011-03-22

    申请号：US11777259

    申请日：2007-07-12

    申请人： Nicolas Gani ,  Meihua Shen ,  Shashank Deshmukh

    发明人： Nicolas Gani ,  Meihua Shen ,  Shashank Deshmukh

    IPC分类号： H01L21/302

    CPC分类号： H01L21/32137 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/823828 ,  H01L29/517

    摘要： Methods for etching, such as for fabricating a CMOS logic gate are provided herein. In some embodiments, a method of etching includes (a) providing a substrate having a first stack and a second stack disposed thereupon, the first stack comprising a high-k dielectric layer, a metal layer formed over the high-k dielectric layer, and a first polysilicon layer formed over the metal layer, the second stack comprising a second polysilicon layer, wherein the first and second stacks are substantially equal in thickness; (b) simultaneously etching a first feature in the first polysilicon layer and a second feature in the second polysilicon layer until the metal layer in the first stack is exposed; (c) simultaneously etching the metal layer and second polysilicon layer to extend the respective first and second features into the first and second stacks; and (d) etching the high-k dielectric layer.

    摘要翻译： 本文提供了用于制造CMOS逻辑门的蚀刻方法。 在一些实施例中，蚀刻方法包括（a）提供具有第一堆叠和设置在其上的第二堆叠的衬底，第一堆叠包括高k电介质层，形成在高k电介质层上的金属层，以及 形成在所述金属层上的第一多晶硅层，所述第二堆叠包括第二多晶硅层，其中所述第一和第二堆叠体的厚度基本相等; （b）同时蚀刻第一多晶硅层中的第一特征和第二多晶硅层中的第二特征，直到第一堆叠中的金属层暴露; （c）同时蚀刻金属层和第二多晶硅层以将相应的第一和第二特征延伸到第一和第二堆叠中; 和（d）蚀刻高k电介质层。

    SHALLOW TRENCH ISOLATION ETCH PROCESS
    15.
    发明申请
    SHALLOW TRENCH ISOLATION ETCH PROCESS 失效
    SHOWOW TRENCH隔离蚀刻工艺

    公开(公告)号：US20090170333A1

    公开(公告)日：2009-07-02

    申请号：US12325220

    申请日：2008-11-30

    申请人： Hiroki Sasano ,  Meihua Shen ,  Radhika Mani ,  Sunil Srinivasan ,  Daehee Weon ,  Nicolas Gani ,  Shashank Deshmukh ,  Anisul Khan

    发明人： Hiroki Sasano ,  Meihua Shen ,  Radhika Mani ,  Sunil Srinivasan ,  Daehee Weon ,  Nicolas Gani ,  Shashank Deshmukh ,  Anisul Khan

    IPC分类号： H01L21/302

    CPC分类号： H01L21/3065 ,  H01L21/76224

    摘要： Methods for fabricating one or more shallow trench isolation (STI) structures are provided herein. In some embodiments, a method for fabricating one or more shallow trench isolation (STI) structures may include providing a substrate having a patterned mask layer disposed thereon to define one or more STI structures. The substrate may be etched using a plasma formed from a process gas mixture to form one or more STI structures on the substrate, wherein the process gas mixture comprises a fluorine-containing gas and either a fluorocarbon-containing gas or a hydrofluorocarbon-containing gas.

    摘要翻译： 本文提供了制造一个或多个浅沟槽隔离（STI）结构的方法。 在一些实施例中，用于制造一个或多个浅沟槽隔离（STI）结构的方法可以包括提供具有设置在其上以限定一个或多个STI结构的图案化掩模层的衬底。 可以使用由工艺气体混合物形成的等离子体来蚀刻衬底，以在衬底上形成一个或多个STI结构，其中工艺气体混合物包含含氟气体和含氟烃气体或含氢氟烃的气体。

    Etching high K dielectrics with high selectivity to oxide containing layers at elevated temperatures with BC13 based etch chemistries
    16.
    发明授权
    Etching high K dielectrics with high selectivity to oxide containing layers at elevated temperatures with BC13 based etch chemistries 有权
    用BC13基蚀刻化学法在高温下蚀刻具有高含氧层的高K电介质

    公开(公告)号：US08722547B2

    公开(公告)日：2014-05-13

    申请号：US11736562

    申请日：2007-04-17

    申请人： Radhika Mani ,  Nicolas Gani ,  Wei Liu ,  Meihua Shen ,  Shashank C. Deshmukh

    发明人： Radhika Mani ,  Nicolas Gani ,  Wei Liu ,  Meihua Shen ,  Shashank C. Deshmukh

    IPC分类号： H01L21/31 ,  H01L21/311 ,  H01L29/51

    CPC分类号： H01L21/31116 ,  H01L21/31122 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

    摘要： Wafers having a high K dielectric layer and an oxide or nitride containing layer are etched in an inductively coupled plasma processing chamber by applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 100° C. and 350° C., and etching the wafer with a selectivity of high K dielectric to oxide or nitride greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a reactive ion etch processing chamber by applying a bias power to the wafer, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a an inductively coupled plasma processing chamber by applying a bias power to the wafer, applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1.

    摘要翻译： 在电感耦合等离子体处理室中蚀刻具有高K电介质层和含氧化物或氮化物层的晶片，通过施加源电力来产生电感耦合等离子体，将包含BCl 3的气体引入室中，设定晶片的温度 在100℃至350℃之间，并且以大于10:1的氧化物或氮化物的高K电介质的选择性蚀刻晶片。 具有氧化物层和氮化物层的晶片通过向晶片施加偏置功率而在反应离子蚀刻处理室中被蚀刻，将包括BCl 3的气体引入室中，将晶片的温度设定在20℃至 并且以大于10:1的氧化物至氮化物选择性蚀刻晶片。 在电感耦合等离子体处理室中蚀刻具有氧化物层和氮化物层的晶片，通过向晶片施加偏置功率，施加源电力以产生电感耦合等离子体，将包括BCl 3的气体引入室中， 晶片的温度在20℃和200℃之间，并且以大于10:1的氧化物至氮化物选择性蚀刻晶片。

    Shallow trench isolation etch process
    17.
    发明授权
    Shallow trench isolation etch process 失效
    浅沟槽隔离蚀刻工艺

    公开(公告)号：US08133817B2

    公开(公告)日：2012-03-13

    申请号：US12325220

    申请日：2008-11-30

    申请人： Hiroki Sasano ,  Meihua Shen ,  Radhika Mani ,  Sunil Srinivasan ,  Daehee Weon ,  Nicolas Gani ,  Shashank Deshmukh ,  Anisul Khan

    发明人： Hiroki Sasano ,  Meihua Shen ,  Radhika Mani ,  Sunil Srinivasan ,  Daehee Weon ,  Nicolas Gani ,  Shashank Deshmukh ,  Anisul Khan

    IPC分类号： H01L21/302

    CPC分类号： H01L21/3065 ,  H01L21/76224

    摘要： Methods for fabricating one or more shallow trench isolation (STI) structures are provided herein. In some embodiments, a method for fabricating one or more shallow trench isolation (STI) structures may include providing a substrate having a patterned mask layer disposed thereon to define one or more STI structures. The substrate may be etched using a plasma formed from a process gas mixture to form one or more STI structures on the substrate, wherein the process gas mixture comprises a fluorine-containing gas and either a fluorocarbon-containing gas or a hydrofluorocarbon-containing gas.

    摘要翻译： 本文提供了制造一个或多个浅沟槽隔离（STI）结构的方法。 在一些实施例中，用于制造一个或多个浅沟槽隔离（STI）结构的方法可以包括提供具有设置在其上以限定一个或多个STI结构的图案化掩模层的衬底。 可以使用由工艺气体混合物形成的等离子体来蚀刻衬底，以在衬底上形成一个或多个STI结构，其中工艺气体混合物包含含氟气体和含氟烃气体或含氢氟烃的气体。

    ETCHING AND PASSIVATING FOR HIGH ASPECT RATIO FEATURES
    19.
    发明申请
    ETCHING AND PASSIVATING FOR HIGH ASPECT RATIO FEATURES 审中-公开
    用于高比例特征的蚀刻和钝化

    公开(公告)号：US20080286978A1

    公开(公告)日：2008-11-20

    申请号：US11749957

    申请日：2007-05-17

    申请人： Rong Chen ,  Tae Won Kim ,  Nicolas Gani ,  Anisul H. Khan

    发明人： Rong Chen ,  Tae Won Kim ,  Nicolas Gani ,  Anisul H. Khan

    IPC分类号： H01L21/302

    CPC分类号： H01L21/30655

    摘要： An etch method includes etching a masked substrate to form a recess with a first sidewall in the substrate. A thin surface layer of the substrate on the first sidewall is then converted into a passivation layer. The masked substrate is etched again to deepen the recess in the substrate. A surface layer of the substrate on the second sidewall of the recess is then converted into a passivation layer. In one embodiment, upon removal of the passivation layers from both sidewalls, the first and second sidewalls of the high aspect ratio recess are aligned to within 10 Å of each other to provide a high aspect ratio recess having a vertical profile.

    摘要翻译： 蚀刻方法包括蚀刻被掩蔽的衬底以在衬底中形成具有第一侧壁的凹部。 然后将第一侧壁上的衬底的薄表面层转换成钝化层。 再次蚀刻掩蔽的衬底以加深衬底中的凹部。 然后将凹槽的第二侧壁上的衬底的表面层转换成钝化层。 在一个实施例中，在从两个侧壁去除钝化层时，高纵横比凹槽的第一和第二侧壁彼此对准，以提供具有垂直剖面的高纵横比凹槽。