公开(公告)号：US20240413067A1

公开(公告)日：2024-12-12

申请号：US18360826

申请日：2023-07-28

Applicant: Unimicron Technology Corp.

Inventor： Chia-Yu PENG ,  Kai-Ming YANG ,  Pu-Ju LIN ,  Cheng-Ta KO

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31

Abstract: An electronic package module including a circuit substrate, an electronic component disposed on the circuit substrate and a molding compound is provided. The molding compound encapsulates the circuit substrate and the electronic component. The circuit substrate includes a first circuit layer and a first insulation layer covering on the first circuit layer. The first insulation layer has a boundary surface where a second circuit layer is disposed. A second insulation layer covers a part of the second circuit layer while the insulation layer bares a region surrounding the perimeter of the boundary surface. The molding compound directly contacts the region and the second insulation layer.

公开(公告)号：US20220068742A1

公开(公告)日：2022-03-03

申请号：US17453489

申请日：2021-11-04

Applicant: Unimicron Technology Corp.

Inventor： Cheng-Hui WU ,  Jeng-Ting LI ,  Ping-Tsung LIN ,  Kai-Ming YANG ,  Pu-Ju LIN ,  Cheng-Ta KO

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56

Abstract: A chip package includes a redistribution layer, a chip, and an encapsulation member. The redistribution layer includes an insulation part, a plurality of first pads and a plurality of second pads, where the insulation part has a first surface, a second surface opposite to the first surface, and a side surface between the first surface and the second surface. The first pads and the second pads are located at the first surface and the second surface respectively. The chip is disposed on the first surface and electrically connected to the first pads. The encapsulation member wraps the chip and the redistribution layer, and covers the first surface and the side surface, where the encapsulation member exposes the second pads, and the encapsulation member is not flush with the first surface and the side surface.

公开(公告)号：US20180332700A1

公开(公告)日：2018-11-15

申请号：US15590020

申请日：2017-05-09

Applicant: Unimicron Technology Corp.

Inventor： Ra-Min TAIN ,  Kai-Ming YANG ,  Chien-Tsai LI

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0209 ,  H05K1/114 ,  H05K2201/0116 ,  H05K2201/0195 ,  H05K2201/041

Abstract: A circuit board includes a first dielectric layer, a first circuit layer, a second circuit layer, a plurality of conductive vias, a second dielectric layer, a patterned seed layer, and a plurality of bonding layers. The first circuit layer is disposed in the first dielectric layer. The second circuit layer is disposed on the first dielectric layer. The conductive vias are disposed in the first dielectric layer and connect the first circuit layer to the second circuit layer. The second dielectric layer is disposed on the first dielectric layer and the second circuit layer and has a plurality of openings to expose a plurality of parts of the second circuit layer. The patterned seed layer is disposed on the exposed parts of second circuit layer and sidewalls of the openings. The bonding layers are respectively disposed on the patterned seed layer and made of porous copper.

公开(公告)号：US20170374748A1

公开(公告)日：2017-12-28

申请号：US15701435

申请日：2017-09-11

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming YANG ,  Chen-Hao LIN ,  Wang-Hsiang TSAI ,  Cheng-Ta KO

IPC: H05K3/40 ,  H05K1/14 ,  H01L21/48 ,  H01L23/14 ,  H01L23/15 ,  H05K1/18 ,  H01L23/498 ,  H05K1/11 ,  H01L21/768

CPC classification number: H05K3/4038 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/145 ,  H01L23/147 ,  H01L23/15 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/37001 ,  H05K1/0271 ,  H05K1/11 ,  H05K1/112 ,  H05K1/142 ,  H05K1/183 ,  H05K3/4673 ,  H05K3/4682 ,  H05K3/4694 ,  H05K2201/10674 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49165

Abstract: A package structure includes a metal layer, a composite layer of a non-conductor inorganic material and an organic material, a sealant, a chip, a circuit layer structure, and an insulating protective layer. The composite layer of the non-conductor inorganic material and the organic material is disposed on the metal layer. The sealant is bonded on the composite layer of the non-conductor inorganic material and the organic material. The chip is embedded in the sealant, and the chip has electrode pads. The circuit layer structure is formed on the sealant and the chip. The circuit layer structure includes at least one dielectric layer and at least one circuit layer. The dielectric layer has conductive blind holes. The insulating protective layer is formed on the circuit layer structure. The insulating protective layer has openings, so as to expose parts of the surface of the circuit layer structure in the openings.